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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
1. DESCRIPTION
The M306H2FCFP is single-chip microcomputer using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 116-pin plastic molded QFP. This single-chip microcomputer operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, this is capable of executing instructions at high speed. This also features a built-in data acquisition circuit, making this correspondence to Teletext broadcasting service.
1.1 Features
* Memory capacity.................................. 128K bytes 5K bytes * Shortest instruction execution time ...... 100 ns (f(XIN)=10 MHz) * Supply voltage ..................................... 4.75 V to 5.25V(at f(XIN)=10 MHz) 2.80V to 5.25V(at f(XCIN)=32kHZ, only in low power dissipation mode) * Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software interrupt sources; 7 levels (Including key input interrupt) * Multifunction 16-bit timer ...................... 5 output timers + 6 input timers * Serial I/O .............................................. 5 channels UART/clock synchronous: 3 Clock synchronous: 2 * DMAC .................................................. 2 channels (trigger: 24 sources) * A-D converter ....................................... 8 bits X 8 channels (Expandable up to 10 channels) * D-A converter ....................................... 8 bits X 2 channels * CRC calculation circuit ......................... 1 circuit * Watchdog timer .................................... 1 line * Programmable I/O ............................... 87 lines _______ * Input port .............................................. 1 port (P85 shared with NMI pin) * Output port ........................................... 1 port (P11 shared with SLICEON pin) * Chip select output ................................ 4 lines * Clock generating circuit ....................... 2 built-in circuits (built-in feedback resistor, and external ceramic or crystal oscillator) * Data acquisition circuit ......................... For PDC, VPS, EPG-J, XDS and WSS
1.2 Applications
VCR, etc
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table of contents
1. DESCRIPTION ...................................................... 1 1.1 Features ........................................................... 1 1.2 Applications ..................................................... 1 1.3 Pin Configuration ............................................. 3 1.4 Block Diagram ................................................. 4 1.5 Performance Outline ........................................ 5 2. OPERATION OF FUNCTIONAL BLOCKS ............ 9 2.1 Memory ............................................................ 9 2.2 Central Processing Unit (CPU) ........................ 13 2.3 Reset ............................................................... 16 2.4 Processor Mode ............................................... 20 2.5 Clock Generating Circuit .................................. 31 2.6 Protection ......................................................... 40 2.7 Interrupt ........................................................... 41 2.8 Watchdog Timer .............................................. 61 2.9 DMAC .............................................................. 63 2.10 Timer .............................................................. 73 2.11 Serial I/O ........................................................ 91 2.12 A-D Converter ................................................ 132 2.13 D-A Converter ................................................ 142 2.14 CRC Calculation Circuit ................................. 144 2.15 Expansion Function ....................................... 146 2.16 Programmable I/O Ports ................................ 170 3. USAGE PRECAUTION .......................................... 180 4. ELECTRICAL CHARACTERISTICS ...................... 185 5. FLASH MEMORY .................................................. 203 5.1 Outline Performance ........................................ 203 5.2 Flash Memory mode ........................................ 204 5.3 CPU Rewrite Mode .......................................... 205 5.4 Functions To Inhibit Rewriting Flash Memory Version ....... 215 5.5 Parallel I/O Mode ............................................. 217 5.6 Standard serial I/O mode ................................. 218 5.7 Absolute maximum ratings .............................. 246 6. PACKAGE OUTLINE ............................................. 248 7. DIFFERENCES BETWEEN M306H2MC-XXXFP AND M306H2FCFP .... 249
Rev. 1.0
2
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
1.3 Pin Configuration
Figures 1.3.1 shows the pin configuration (top view).
P21/A1(/D1/D0)
P22/A2(/D2/D1) P23/A3(/D3/D2)
P24/A4(/D4/D3) P25/A5(/D5/D4)
P26/A6(/D6/D5) P27/A7(/D7/D6)
P14/D12 P15/D13/INT3 P16/D14/INT4
P17/D15/INT5
P20/A0(/D0/-)
P30/A8(/-/D7)
P12/D10
P13/D11
VCC P31/A9 P32/A10 P33/A11
P37/A15
P35/A13 P36/A14
P34/A12
P40/A16 P41/A17
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
P42/A18
P10/D8
P11/D9
VSS
P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC P97/ADTRG/SIN4 VDD1 SYNCIN SVREF VSS1 VDD3 CVIN1 VSS3 FSCIN P96/ANEX1/SOUT4
88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
58 57 56 55 54 53 52 51 50 49 48 47 46
P43/A19
P44/CS0
P45/CS1
P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RXD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RXD1 P67/TXD1 P11/SLICEON
M306H2FCFP
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
M1 M2
VDD2 LP4 LP3 LP2 VSS2
CNVss
P92/TB2IN/SOUT3 P91/TB1IN/SIN3
P87/XCIN
RESET XOUT
Vss XIN
P95/ANEX0/CLK4
P90/TB0IN/CLK3 BYTE
P93/DA0/TB3IN
P86/XCOUT
Vcc
P77/TA3IN P76/TA3OUT
P73/CTS2/RTS2/TA1IN
P80/TA4OUT
116P6A-A
Figure 1.3.1 Pin configuration (top view)
Rev. 1.0
3
P71/RXD2/SCL/TA0IN/TB5IN P70/TXD2/SDA/TA0OUT
P94/DA1/TB4IN
P81/TA4IN
P85/NMI
P84/INT2
P83/INT1 P82/INT0
P72/CLK2/TA1OUT
P75/TA2IN P74/TA2OUT
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
1.4 Block Diagram
Figure 1.4.1 is a block diagram of the M306H2FCFP.
8 8 8 8 8 8 8
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
8
Internal peripheral functions
Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits)
A-D converter
( 8 bits X 8 channels
Expandable up to 10 channels)
System clock generator XIN-XOUT XCIN-XCOUT
Clock synchronous SI/O
Port P8
7
UART/clock synchronous SI/O
(8 bits X 3 channels)
CRC arithmetic circuit (CCITT )(Polynomial : X16+X12+X5+1)
(8 bits X 2 channels)
Port P85
Data acquisition controller
M16C/60 series16-bit CPU core
Registers Program counter PC Stack pointer ISP USP Vector table INTB Flag register SB FLG
Memory
ROM (128K bytes) RAM (5K bytes)
Port P9
Watchdog timer
(15 bits)
8
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB
Port P10
8
Multiplier
Port P11
Figure 1.4.1 Block diagram of M306H2FCFP
Rev. 1.0
4
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
1.5 Performance Outline
Table 1.5.1 is a performance outline of M306H2FCFP. Table 1.5.1 Performance outline of M306H2FCFP Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port P0 to P10 (except P85) Input port P85 Output port P11 Multifunction TA0, TA1, TA2, TA3, TA4 timer TB0, TB1, TB2, TB3, TB4, TB5 Serial I/O UART0, UART1, UART2 SI/O3, SI/O4 A-D converter D-A converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock generating circuit Supply voltage Device configuration Package Data acquisition Slice RAM Data acquisition circuit Performance 91 instructions 100ns (f(XIN)=10MHZ) 128K bytes 5K bytes 8 bits 10, 7 bits 1 1 bit 1 1 bit 1 16 bits 5 16 bits 6 (UART or clock synchronous) x 3 (Clock synchronous) x 2 8 bits (8 + 2) channels 8 bits 2 channels 2 channels (trigger: 24 sources) CRC-CCITT 15 bits 1 (with prescaler) 25 internal and 8 external sources, 4 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or crystal oscillator) 4.75V to 5.25V (at f(XIN)=10MHZ) 2.80V to 5.25V(at f(XCIN)=32kHZ, Only low power dissipation mode) CMOS high performance silicon gate 116-pin plastic mold QFP 864 Bytes (48 18 8-bit) for PDC, VPS, EPG-J, XDS and WSS
Rev. 1.0
5
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 1.5.2 Pin Description
Pin name VCC, VSS CNVSS RESET XIN XOUT Signal name Power supply input CNVSS Reset input Clock input Clock output Input Input Input Output I/O type Function Supply 4.75 to 5.25 V to the Vcc pin. Supply 0 V to the Vss pin. Connect this pin to VSS. A "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an external data bus. A 16-bit width is selected when this input is "L"; an 8-bit width is selected when this input is "H". This input must be fixed to either "H" or "L". Connect this pin to the VSS pin when not using external data bus. This pin is a power supply input for the A-D converter. Connect this pin to VCC. This pin is a power supply input for the A-D converter. Connect this pin to VSS. This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in signal-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion mode, selection of the internal pull-resistor in not available. When set as a separate bus, these pins input and output data (D0-D7). This is an 8-bit I/O port equivalent to P0. Pins in this port also function as external interrupt pins as selected by software. When set as a separate bus, these pins input and output data (D8-D15). This is an 8-bit I/O port equivalent to P0. These pins output 8 low-order address bits (A0-A7). If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0-D7) and output 8 low-order address bits (A0-A7) separated in time by multiplexing. If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D0-D6) and output address (A1-A7) separated in time by multiplexing. They also output address (A 0). This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A8-A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A 9-A15). This is an 8-bit I/O port equivalent to P0. These pins output CS0-CS3 signals and A16-A19. CS0-CS3 are chip select signals used to specify an access space. A16-A19 are 4 highorder address bits.
BYTE
External data bus width select input Analog power supply input Analog power supply input Reference voltage input I/O port P0
Input
AVCC AVSS VREF P00 to P07
Input Input/output
D0 to D7 P10 to P17 I/O port P1
Input/output Input/output
D8 to D15 P20 to P27 A0 to A7 A0/D0 to A7/D7 A0, A1/D0 to A7/D6 P30 to P37 A8 to A15 A8/D7, A9 to A15 P40 to P47 CS0 to CS3, A16 to A19 I/O port P4 I/O port P3 I/O port P2
Input/output Input/output Output Input/output
Output Input/output Input/output Output Input/output Output Input/output Output Output
Rev. 1.0
6
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 1.5.3 Pin Description
Pin name P50 to P57 Signal name I/O port P5 I/O type Input/output Function This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is "L" and to the odd addresses when the WRH signal is "L". Data is read when RD is "L". WR, BHE, and RD selected Data is written when WR is "L". Data is read when RD is "L". Odd addresses are accessed when BHE is "L". Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is "L", the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a "L" level. ALE is used to latch the address. While the input level of the RDY pin is "L", the microcomputer is in the ready state.
WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY
Output Output Output Output Output Input Output Input
P60 to P67
I/O port P6
Input/output
This is an 8-bit I/O port equivalent to P0. When used input in singlechip and memory expansion modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0-A3, timer B5 or UART2 I/O pins as selected by software. P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P8 6 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from "H" to "L". The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as SI/O3, 4 I/O pins, Timer B0-B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins. Furthermore, P104-P107 also function as input pins for the key input interrupt function. This is a 1-bit output-only port. Pins in this port also function as SLICEON output pins as selected by software.
P70 to P77
I/O port P7
Input/output
P80 to P84, P86, P87, P85
I/O port P8
Input/output Input/output Input/output Input
I/O port P85
P90 to P97
I/O port P9
Input/output
P100 to P107
I/O port P10
Input/output
P11
Output port P11 Output
Rev. 1.0
7
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 1.5.4 Pin Description
Pin name
VDD1, VSS1 VDD2, VSS2 VDD3, VSS3
Signal name
Power supply input Power supply input Power supply input
I/O type
Function
Digital power supply pin. Supply 4.75 to 5.25 V to the VDD1 pin. Supply 0 V to the VSS1 pin. Analog power supply pin. Supply 4.75 to 5.25 V to the V DD2 pin. Supply 0 V to the V SS2 pin Analog power supply pin. Supply 4.75 to 5.25 V to the VDD3 pin. Supply 0 V to the V SS3 pin
SVREF
Synchronous Input slice level input Composite video signal input 1
Composite video signal input 2 Chip mode setting input
Filter output 1 Filter output 2
Filter output 3
When slice the vertical synchronous signal, input slice power.
CVIN1
Input
This pin inputs the external composite video signal. Data slices this signal internally by setting.
This pin inputs the external composite video signal. Synchronous devides this signal internally.
SYNCIN
Input
M1 LP2 LP3
LP4
Input Output Output
Output
Usually, supply 0 V to the pin. This is a filter output pin 1 (for fSC). This is a filter output pin 2 (for VPS).
This is a filter output pin 3 (for PDC).
FSCIN
fsc input pin for Input synchronous signal generation
Power supply input for flash rewriting Input
Sub-carrier (fsc) input pin for synchronous signal generation.
M2
It is power supply input pin for rewriting of built-in flash memory. Usually supply 0V to M2 pin, and supply 4.75-5.25V at the time of rewriting of built-in flash memory.
Rev. 1.0
8
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2. OPERATION OF FUNCTIONAL BLOKS
The M306H2MC-XXXFP accommodates certain units in a single chip. These units include RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, Data slicer circuit and I/O ports. The following explains each unit.
2.1 Memory
Figure 2.1.1 is a memory map of the M306H2MC-XXXFP. The address space extends the 1M bytes from address 0000016 to FFFFF16. From address FFFFF16 down is ROM. In the M306H2MC-XXXFP, can use from address from E000016 to FFFFF16 as 128K bytes internal ROM area. The vector table for fixed _______ interrupts such as the reset and NMI are mapped to from address FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. 5K bytes of internal RAM is mapped to from address 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to from address 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 2.1.2 to 2.1.4 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to from address FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode, a part of the spaces are reserved and cannot be used. The following spaces cannot be used. * The space between 0180016 and 03FFF16 (memory expansion mode) * The space between D000016 and DFFFF16 (memory expansion mode)
0000016
003FF16 0040016
SFR area For details, see Figures 2.1.2 to 2.1.4
FFE0016
Internal RAM area
017FF16 0180016 03FFF16 0400016
Internal reserved area (Note)
Special page vector table
External area
D000016 E000016 Internal ROM area FFFFF16 Note : During memory expansion mode, can not be used.
Internal reserved area (Note)
FFFDC16
Undefined instruction
Overflow
BRK instruction Address match Single step Watchdog timer DBC NMI Reset
FFFFF16
Figure 2.1.1 Memory map
Rev. 1.0
9
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316
004416 004516 004616 004716
Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR) Address match interrupt enable register (AIER) Protect register (PRCR)
004816 004916 004A16 004B16 004C16 004D16 004E16 004F16
INT3 interrupt control register(INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT5 interrupt control register(INT5IC) SI/O3 interrupt control register (S3IC) INT4 interrupt control register(INT4IC)
Bus collision detection interrupt control register (BCNIC)
DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC)
UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC)
Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0)
005016 005116 005216 005316 005416 005516 005616
Address match interrupt register 1 (RMAD1)
005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016
Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC)
DMA0 source pointer (SAR0)
020016 020116 020216 020316
DMA0 destination pointer (DAR0)
020416 020516 020616 020716 020816 020916 020A16
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
020B16 020C16 020D16 020E16 020F16
Slice RAM address control register Slice RAM data control register
DMA1 source pointer (SAR1)
021016 021116 021216 021316
DMA1 destination pointer (DAR1)
021416 021516 021616
Address control register for expansion register Data control register for expansion register Humming 8/4 register Humming 24/18 register 0 Humming 24/18 register 1
DMA1 transfer counter (TCR1)
021716 021816 021916 021A16
DMA1 control register (DM1CON)
021B16 021C16 021D16 021E16 021F16 022016
033F16
Note: Location in the SFR area where nothing is allocated are reserved. Do not access these areas for read or write.
Figure 2.1.2 Location of peripheral unit control registers (1)
Rev. 1.0
10
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16
Timer B3, 4, 5 count start flag (TBSR)
038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16
Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 (TA0) Timer A1 (TA1) Timer A2 (TA2) Timer A3 (TA3) Timer A4 (TA4) Timer B0 (TB0) Timer B1 (TB1) Timer B2 (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR)
Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5)
Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) Interrupt cause select register (IFSR) SI/O3 transmit/receive register (S3TRR) SI/O3 control register (S3C) SI/O3 bit rate generator (S3BRG) SI/O4 transmit/receive register (S4TRR) SI/O4 control register (S4C) SI/O4 bit rate generator (S4BRG)
039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Flash memory control register (FER)
UART2 special mode register 3(U2SMR3) UART2 special mode register 2(U2SMR2) UART2 special mode register (U2SMR)
UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB)
03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16
DMA0 request cause select register (DM0SL) DMA1 request cause select register (DM1SL) CRC data register (CRCD) CRC input register (CRCIN)
Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 2.1.3 Location of peripheral unit control registers (2)
Rev. 1.0
11
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7)
A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON)
Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) Port P3 (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 (P8) Port P9 (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10)
Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR)
Note: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 2.1.4 Location of peripheral unit control registers (3)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.2 Central Processing Unit (CPU)
The CPU has 13 registers shown in Figure 2.2.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
b15
b8 b7
b0
R0(Note)
H
L
b15
b8 b7
b0
b19
b0
R1(Note)
H
L Data registers
PC
Program counter
b15
b0
b19
b0
R2(Note)
INTB
H
L
Interrupt table register
b0
b15
b0
b15
R3(Note)
USP
User stack pointer
b15
b0
b15
b0
A0(Note) Address registers
ISP
Interrupt stack pointer
b15
b0
b15
b0
A1(Note)
SB
Static base register
b15
b0
b15
b0
FB(Note)
Frame base registers
FLG
Flag register
IPL
U
I OBS Z DC
Note: These registers consist of two register banks.
Figure 2.2.1 Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev. 1.0
13
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 2.2.2 shows the flag .register (FLG). The following explains the function of each flag: * Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged. * Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0". * Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0". * Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0". * Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged.
Rev. 1.0
14
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
* Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. * Bits 8 to 11: Reserved area * Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. * Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
b15
b0
IPL
U
I
OBSZDC
Flag register (FLG)
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Figure 2.2.2 Flag register (FLG)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.3 Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See "Software Reset" for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 2.3.1 shows the example reset circuit. Figure 2.3.2 shows the reset sequence.
5V 4.75V VCC 0V 5V RESET 0.95V 0V
RESET
VCC
Figure 2.3.1 Example reset circuit
XIN More than 20 cycles are needed
RESET
BCLK 24 cycles
BCLK
Single chip mode Address
Address FFFFC16
Content of reset vector
Address FFFFE16
Figure 2.3.2 Reset sequence
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
____________
Table 2.3.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 2.3.3 and 2.3.4 show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 2.3.1 Pin status when RESET pin level is "L"
Pin name P0 to P10 P11 CVIN1,SVREF,SYNCIN,M1,FSCIN LP2,LP3,LP4
Status Input port (floating) Output port Input port Output port
2.3.1 Software Reset
Writing "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Processor mode register 0 (Note) Processor mode register 1
System clock control register 0
System clock control register 1
Chip select control register
Address match interrupt enable register
Protect register
Watchdog timer control register
Address match interrupt register 0
(000416)***
0016
0
Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Slice RAM address control register
(005A16)*** (005B16)*** (005C16)*** (005D16)*** (005E16)*** (005F16)*** (020E16)*** (020F16)***
?000 ?000 ?000 00?000 00?000 00?000 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
(000516)*** 0 0 0 0 0
(000616)*** 0 1 0 0 1 0 0 0
(000716)*** 0 0 1 0 0 0 0 0
(000816)*** 0 0 0 0 0 0 0 1
(000916)***
(000A16)*** 00
000
(000F16)*** 0 0 0 ? ? ? ? ?
(001016)*** (001116)*** (001216)***
0016
0016
Slice RAM data control register
(021016)*** (021116)***
0000
Address control register for expansion register
Address match interrupt register 1
(001416)***
0016
0016
Data control register for expansion register
(021616)** * (021716)*** (021816)*** (021916)***
(001516)*** (001616)***
DMA0 control register
DMA1 control register
INT3 interrupt control register
Timer B5 interrupt control register
Timer B4 interrupt control register
Timer B3 interrupt control register
SI/O4 interrupt control register
SI/O3 interrupt control register
0000
Humming 8/4 register
(002C16)*** 0 0 0 0 0 ? 0 0
(003C16)*** 0 0 0 0 0 ? 0 0
(004416)***
(004516)***
(004616)***
(004716)***
(004816)***
(004916)***
(021A16)*** (021B16)***
00?000
?000
?000
?000
00?000
00?000
Humming 24/18 register0
(021C16)*** (021D16)***
Humming 24/18 register1
(021E16)*** (021F16)***
Timer B3,4,5 count start flag Timer B3 mode register Timer B4 mode register Timer B5 mode register Interrupt cause select register SI/O3 control register SI/O4 control register UART2 special mode register 2 UART2 special mode register
(034016)*** 0 0 0 (035B16)*** 0 0 ? (035C16)*** 0 0 ? (035D16)*** 0 0 ? (035F16)*** (036216)*** (036616)*** (037616)*** (037716)*** (037816)*** 0000 0000 0000 0016 4016 4016 0016 0016 0016
Bus collision detection interrupt control register
(004A16)***
?000
DMA0 interrupt control register
DMA1 interrupt control register
Key input interrupt control register
A-D conversion interrupt control register
(004B16)***
(004C16)***
(004D16)***
(004E16)***
?000
?000
?000
?000
?000
?000
?000
UART2 transmit interrupt control register (004F16)*** UART2 receive interrupt control register
UART0 transmit interrupt control register UART0 receive interrupt control register
UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register
(005016)***
(005116)*** (005216)***
(005316)*** (005416)*** (005516)*** (005616)*** (005716)*** (005816)*** (005916)***
UART2 transmit/receive mode register
?000
UART2 transmit/receive control register 0 (037C16)*** 0 0 0 0 1 0 0 0 (037D16)*** 0 0 0 0 0 0 1 0
?000
UART2 transmit/receive control register 1
?000
?000
?000
?000
?000
?000
x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Figure 2.3.3 Device's internal status after a reset is cleared
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Count start flag
(038016)***
0016
D-A control register Port P0 direction register
(03DC16)*** (03E216)*** (03E316)*** (03E616)*** (03E716)*** (03EA16)*** (03EB16)*** (03EE16)*** (03EF16)*** (03F216)*** 0 0 (03F316)*** (03F616)*** (03FC16)*** (03FD16)*** (03FE16)*** (03FF16)***
0016 0016 0016 0016 0016 0016 0016 0016 0016 00000 0016 0016 0016 0016 0016 0016 000016 000016 000016 0000016 000016 000016 000016 000016
Clock prescaler reset flag
One-shot start flag Trigger select flag Up-down flag Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register
(038116)*** 0
(038216)*** 0 0 (038316)*** (038416)*** (039616)*** (039716)*** (039816)*** (039916)*** (039A16)*** (039B16)*** 0 0 ? (039C16)*** 0 0 ? (039D16)*** 0 0 ?
00000
0016
Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Port P9 direction register Port P10 direction register Pull-up control register 0 Pull-up control register 1(Note) Pull-up control register 2 Port control register Data registers (R0/R1/R2/R3) Address registers (A0/A1) Frame base register (FB) Interrupt table register (INTB) User stack pointer (USP) Interrupt stack pointer (ISP)
0016
0016
0016
0016
0016
0016 0000
0000
0000
UART0 transmit/receive mode register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1
(03A016)***
0016
(03A416)*** 0 0 0 0 1 0 0 0 (03A516)*** 0 0 0 0 0 0 1 0
UART1 transmit/receive mode register
(03A816)***
0016
UART1 transmit/receive control register 0 (03AC16)*** 0 0 0 0 1 0 0 0 UART1 transmit/receive control register 1 (03AD16)*** 0 0 0 0 0 0 1 0 UART transmit/receive control register 2 DMA0 cause select register DMA1 cause select register (03B016)*** (03B816)*** (03BA16)***
0000000
0016
0016
A-D control register 2 A-D control register 0 A-D control register 1
(03D416)*** 0 0 0 0
0
Static base register (SB) Flag register (FLG)
(03D616)*** 0 0 0 0 0 ? ? ? (03D716)***
0016
x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset.
Figure 2.3.4 Device's internal status after a reset is cleared
Rev. 1.0
19
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.4 Processor Mode (1) Types of Processor Mode
Processor mode can be used at microprocessor mode. One of three processor modes can be selected:single-chip mode and memory expansion mode.The functions of some pins,the memory map,and the access space differ according to the selected processor mode. * Single-chip mode In single-chip mode,only internal memory space (SFR,internal RAM,and internal ROM)can be accessed.Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. * Memory expansion mode In memory expansion mode,external memory can be accessed in addition to the internal memory space (SFR,internal RAM,and internal ROM). In this mode,some of the pins function as the address bus,the data bus,and as control signals.The number of pins assigned to these functions depends on the bus and register settings.(See "Bus Settings " for details..)
(2) Setting Processor Modes
The processor mode is set using the processor mode bits (bits 1 and 0 at address 000416).Do not set the processor mode bits to "102 " and "112 ". Changing the processor mode bits selects the mode.Therefore, never change the processor mode bits when changing the contents of other bits. * Applying VSS to CNVSS pin The microcomputer begins operation in single-chip mode after being reset.Memory expansion mode is selected by writing "012 " to the processor mode is selected bits.. Figure 2.4.1 shows the processor mode register 0 and 1. Figure 2.4.2 shows the memory maps applicable for each of the modes when memory area dose not be expanded (normal mode). Note : Microprocessor mode cannot be used.
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PM0
Address 000416
When reset 0016
Bit symbol
PM00 PM01 PM02 PM03
Bit name
Processor mode bit
b1 b0
Function
0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Inhibited 1 1: Inhibited 0 : RD,BHE,WR 1 : RD,WRH,WRL The device is reset when this bit is set to "1". The value of this bit is "0" when read.
b5 b4
RW
R/W mode select bit Software reset bit
PM04 PM05 PM06
Multiplexed bus space select bit
0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note 3) 0 : Address output 1 : Port function (Address is not output) 0 : BCLK is output 1 : BCLK is not output (Pin is left floating)
Port P40 to P43 function select bit (Note 2) BCLK output disable bit
PM07
Notes 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. 2: Valid in memory expansion mode. 3: If the entire space is of multiplexed bus in memory expansion mode, chose an 8bit width. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be in used in each chip select.
Processor mode register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
00
0
Symbol PM1
Address 000516
When reset 00000XX02
Bit symbol
Reserved bit Nothing is assigned.
Bit name
Function
Must always be set to "0"
RW
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Reserved bit Reserved bit PM17 Wait bit Must always be set to "0" Must always be set to "0" 0 : No wait state 1 : Wait state inserted
Note : Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Figure 2.4.1 Processor mode registers
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Single-chip mode
0000016
Memory expansion mode
SFR area
0040016
SFR area Internal RAM area
Internally reserved area
Internal RAM area
017FF16
0400016
Inhibited
External area
Internally reserved area
D000016 E000016
Internal ROM area
FFFFF16
Internal ROM area
External area : Accessing this area allows the user to access a device connected externally to the microcomputer.
Figure 2.4.2 Memory maps in each processor mode
Rev. 1.0
22
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.4.1 Bus settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings.Table 2.4.1 shows the factors used to change the bus settings. Table 2.4.1 Factors for switching bus settings Bus setting Switching external address bus width Switching external data bus width Switching between separate and multiplex bus Switching factor Bit 6 of processor mode register 0 BYTE pin Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to "1", the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to "0", the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus. (2) Selecting external data bus width The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is "L", the bus width is set to 16 bits; when "H", it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to "H" or to "L". (3) Selecting separate/multiplex bus The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. * Separate bus In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is "H", the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is "L", the data bus is set to 16 bits and P0 and P1 are both used for the data bus. When the separate bus is used for access, a software wait can be selected. * Multiplex bus In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin = "H"), the 8 bits from D0 to D7 are multiplexed with A0 to A7. With a 16-bit data bus selected (BYTE pin = "L"), the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer's even addresses (every 2nd address). To access these external devices, access the even addresses as bytes. The ALE signal latches the address. It is output from P56. Before using the multiplex bus for access, be sure to insert a software wait. If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The higher-order address become a port of the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
Rev. 1.0
23
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 2.4.2 Pin functions for processor mode
Processor mode Single-chip mode Memory expansion mode
"01" Multiplexed bus space select bit Either CS1 or CS2 is for multiplexed bus and others are for separate bus 8 bits "H" I/O port I/O port I/O port I/O port
/data bus (Note)
Memory expansion mode "00" "11"(Note 1) Multiplexed bus for the entire space 8 bits "H" I/O port I/O port Address bus
/data bus
(separate bus)
Data bus width BYTE pin level P00 to P07 P10 to P17 P20 P21 to P27 P30 P31 to P37 P40 to P43 Port P40 to P43 function select bit = 1 P40 to P43 Port P40 to P43 function select bit = 0 P44 to P47 P50 to P53
16 bits "L" Data bus Data bus Address bus
Address bus
8 bits "H" Data bus I/O port Address bus Address bus Address bus Address bus I/O port
16 bits "L" Data bus Data bus Address bus Address bus
/data bus
Data bus I/O port
Address bus /data bus (Note) Address bus /data bus (Note)
Address bus
Address bus A8/D7 I/O port I/O port
I/O port
/data bus (Note)
Address bus
Address bus Address bus I/O port
I/O port I/O port
Address bus I/O port
Address bus I/O port
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
I/O port I/O port
CS (chip select) or programmable I/O port
(For details, refer to "Bus control")
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK (For details, refer to "Bus control") HLDA HOLD ALE HLDA HOLD ALE HLDA HOLD ALE HLDA HOLD ALE HLDA HOLD ALE
P54 P55 P56
I/O port I/O port I/O port
P57
I/O port
RDY
RDY
RDY
RDY
RDY
Note 1: If the entire space is of multiplexed bus in memory expansion mode, chose an 8-bit width. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. 2: Address bus when in separate bus mode.
Rev. 1.0
24
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.4.2 Bus Control
The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes. (1) Address bus/data bus The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is "H", the 8 ports D0 to D7 function as the data bus. When BYTE is "L", the 16 ports D0 to D15 function as the data bus. When a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) Chip select signal The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode. IN single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control register. Figure 2.4.3 shows the chip select control register. The chip select signal can be used to split the external area. Tables 2.4.3 show the external memory areas specified using the chip select signal. Table 2.4.3 External areas specified by the chip select signals
Processor mode CS0 3000016 to CFFFF16 (640K bytes)
Chip select signal
CS1 2800016 to 2FFFF16 (32K bytes) CS2 0800016 to 27FFF16 (128K bytes) CS3 0400016 to 07FFF16 (16K bytes)
Memory expansion mode
Chip select control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CSR
Address 000816
When reset 0116
Bit symbol
CS0 CS1 CS2 CS3 CS0W CS2W CS2W CS3W
Bit name
CS0 output enable bit CS1 output enable bit CS2 output enable bit CS3 output enable bit CS0 wait bit CS1 wait bit CS2 wait bit CS3 wait bit
Function
0 : Chip select output disabled (Normal port pin) 1 : Chip select output enabled
RW
0 : Wait state inserted 1 : No wait state
Figure 2.4.3 Chip select control register
Rev. 1.0
25
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) Read/write signals With a 16-bit data bus (BYTE pin ="L"), bit 2 of the processor mode register 0 (address 000416) select
_____ ________ ______ _____ ________ _________
the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus _____ ______ _______ (BYTE pin = "H"), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to "0".) Tables 2.4.4 and 2.4.5 show the operation of these signals. _____ ______ ________ After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. _____ _________ _________ When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note). Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to "1".
_____ ________ _________
Table 2.4.4 Operation of RD, WRL, and WRH signals
Data bus width 16-bit (BYTE = "L") RD L H H H WRL H L H L WRH H H L L Status of external data bus Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses
_____
______
________
Table 2.4.5 Operation of RD, WR, and BHE signals
Data bus width RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of external data bus Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data
16-bit (BYTE = "L")
8-bit (BYTE = "H")
(4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls.
When BYTE pin = "H" ALE D0/A0 to D7/A7 A8 to A19 Address Data (Notes 1)
When BYTE pin = "L" ALE A0 D0/A1 to D7/A8 Address (Notes 2) A9 to A19 Address Address Address Data (Notes 1)
Notes 1: Floating when reading Notes 2: When multiplexed bus for the entire space is selected,these are I/O ports.
Figure 2.4.4 ALE signal and address/data bus
Rev. 1.0
26
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
________
(5) The RDY signal ________ RDY is a signal that facilitates access to an external device that requires long access time. As shown ________ in Figure 2.4.5, if an "L" is being input to the RDY at the BCLK falling edge, the bus turns to the wait ________ state. If an "H" is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 2.4.6 shows the state of the microcomputer with the bus in the wait state, and Figure 2.4.5 ____ ________ shows an example in which the RD signal is prolonged by the RDY signal. ________ The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of ________ the chip select control register (address 000816) are set to "0". The RDY signal is invalid when setting ________ "1" to all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using. Table 2.4.6 Microcomputer status in ready state (Note) Item Oscillation
___ _____
Status On
________
R/W signal, address bus, data bus, CS __________ ALE signal, HLDA, programmable I/O ports Internal peripheral circuits
________
Maintain status when RDY signal received On
Note: The RDY signal cannot be received immediately prior to a software wait.
In an instance of separate bus
BCLK
RD CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
: Wait using RDY signal : Wait using software
_____
Accept timing of RDY signal
________
Figure 2.4.5 Example of RD signal extended by RDY signal
Rev. 1.0
27
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" __________ to the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This __________ __________ status is maintained and "L" is output from the HLDA pin as long as "L" is input to the HOLD pin. Table 2.4.7 shows the microcomputer status in the hold state. __________ Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 2.4.6 Bus-using priorities Table 2.4.7 Microcomputer status in hold state Item Oscillation
___ _____ _______
Status ON Floating Floating Maintains status when hold signal is received Output "L" ON (but watchdog timer stops) Undefined
R/W signal, address bus, data bus, CS, BHE Programmable I/O ports P0, P1, P2, P3, P4, P5 P6, P7, P8, P9, P10
__________
HLDA Internal peripheral circuits ALE signal
(7) External bus status when the internal area is accessed Table 2.4.8 shows the external bus status when the internal area is accessed.
Table 2.4.8 External bus status when the internal area is accessed
Item Address bus SFR accessed Address output Internal RAM accessed Maintain status before accessed address of external area Data bus When read When write RD, WR, WRL, WRH BHE Floating Output data RD, WR, WRL, WRH output BHE output Floating Undefined Output "H" Maintain status before accessed status of external area CS ALE Output "H" Output "L" Output "H" Output "L"
Rev. 1.0
28
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(8) BCLK output The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note). When set to "1", the output floating. Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protectregister (address 000A16) to "1". (9) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) and bits 4 to 7 of the chip select control register (address 000816). A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the wait bit of the processor mode register 1. When set to "0", each bus cycle is executed in one BCLK cycle. When set to "1", each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to "0". When set to "1", a wait is applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring to the recommended operating conditions (main clock input oscillation fre________ quency) of the electric characteristics. However, when the user is using the RDY signal, the relevant bit in the chip select control register's bits 4 to 7 must be set to "0". When the wait bit of the processor mode register 1 is "0", software waits can be set independently for each areas selected using the chip select signal. Bits 4 to 7 of the chip select control register corre_______ _______ spond to chip selects CS0 to CS3. When one of these bits is set to "1", the bus cycle is executed in one BCLK cycle. When set to "0", the bus cycle is executed in two or three BCLK cycles. These bits default to "0" after the microcomputer has been reset. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also, insert a software wait if using the multiplex bus to access the external memory area. Table 2.4.9 shows the software wait and bus cycles. Figure 2.4.7 shows example bus timing when using software waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to "1". Table 2.4.9 Software waits and bus cycles
Area SFR Internal ROM/RAM Separate bus Separate bus External memory area Separate bus Multiplex bus Multiplex bus Bus status Wait bit Invalid 0 1 0 0 1 0 1 Bits 4 to 7 of chip select control register Invalid Invalid Invalid 1 0 0 (Note) 0 0 (Note) Bus cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles 2 BCLK cycles 3 BCLK cycles 3 BCLK cycles
Note: When using the RDY signal, always set to "0".
Rev. 1.0
29
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
< Separate bus (no wait) >
Bus cycle (Note 1)
BCLK Write signal Read signal
Data bus Address bus (Note 2) Chip select (Note 2)
Output
Input
Address
Address
< Separate bus (with wait) > Bus cycle (Note 1)
BCLK Write signal Read signal
Output Input
Data bus Address bus (Note 2) Chip select (Note 2)
Address
Address
< Multiplexed bus > Bus cycle (Note 1)
BCLK Write signal Read signal ALE Address bus (Note 2) Address bus/ Data bus Chip select (Note 2) Address Address Data output Address Address
Input
Note 1: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Note 2: The address bus and chip select may be extended depending on the CPU status such as that of the instruction queue buffer.
Figure 2.4.7 Typical bus timings using software wait
Rev. 1.0
30
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.5 Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 2.5.1 Main clock and sub clock generating circuits Main clock generating circuit Use of clock * CPU's operating clock source * Internal peripheral units' operating clock source Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other Ceramic or crystal oscillator XIN, XOUT Available Oscillating Sub clock generating circuit * CPU's operating clock source * Timer A/B's count clock source Crystal oscillator XCIN, XCOUT Available Stopped
Externally derived clock can be input
2.5.1 Example of oscillator circuit
Figure 2.5.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 2.5.2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 2.5.1 and 2.5.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XIN
XOUT (Note) Rd
XIN
XOUT Open
Externally derived clock CIN COUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable.Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction.
Figure 2.5.1 Examples of main clock
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XCIN
XCOUT (Note) RCd
XCIN
XCOUT Open
Externally derived clock CCIN CCOUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable.Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction.
Figure 2.5.2 Examples of sub clock
Rev. 1.0
31
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.5.2 Clock Control
Figure 2.5.3 shows the block diagram of the clock generating circuit.
XCIN CM04
XCOUT 1/32
fC32 f1 f1SIO2 fC fAD f8 f32 f8SIO2 f32SIO2
Sub clock CM10 "1" Write signal SQ XIN R RESET Software reset NMI Interrupt request level judgment output WAIT instruction Main clock CM02 CM05 XOUT b a c d Divider
CM07=0 BCLK fC CM07=1
SQ R
b a
1/2 1/2 1/2 1/2 1/2
c
CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10
d
CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16
Details of divider
Figure 2.5.3 Clock generating circuit
Rev. 1.0
32
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expansion and the microprocessor modes. The main clock division select bit 0(bit 6 at address 000616) changes to "1" when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
Rev. 1.0
33
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Figure 2.5.4 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0 Bit symbol
CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07
Address 000616 Bit name
Clock output function select bit (Valid in single-chip mode only) WAIT peripheral function clock stop bit XCIN-XCOUT drive capacity select bit (Note 2) Port XC select bit Main clock (X IN-XOUT) stop bit (Notes 3,4,5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6)
When reset 4816 Function
b1 b0
RW
0 0 : I/O port P5 7 0 1 : Output f c 1 0 : Output f 8 1 1 : Output f 32 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) 0 : LOW 1 : HIGH 0 : I/O port 1 : XCIN-XCOUT generation 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shifting to stop mode and at a reset. Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and operating with X IN, set this bit to "0". When main clock oscillation is operating by itself, set system clock select bit (CM07) to "1" before setting this bit to "1". Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to "1", X OUT turns "H". The built-in feedback resistor remains being connected, so XIN turns pulled up to X OUT ("H") via the feedback resistor. Note 6: Set port Xc select bit (CM04) to "1" and stabilize the sub-clock oscillating before setting to this bit from "0" to "1". Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to "0" and stabilize the main clock oscillating before setting this bit from "1" to "0". Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: fC32 is not included. Do not set this bit to "1" in the low-speed/ low-power dissipation mode. Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol CM1 Bit symbol
CM10
Address 000716 Bit name
All clock stop control bit (Note4)
When reset 2016 Function
0 : Clock on 1 : All clocks off (stop mode) Always set to "0" 0 : LOW 1 : HIGH
b7 b6
RW
Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3)
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A 16) to "1" before writing to this register. Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006 16) is "0". If "1", division mode is fixed at 8. Note 4: If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor is cut off. XCIN and XCOUT turn highimpedance state.
Figure 2.5.4 Clock control registers 0 and 1
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.5.3 Clock output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to "1", the output of f8 and f32 stops when a WAIT instruction is executed.
2.5.4 Stop Mode
Writing "1" to the main clock and sub-clock stop control bit (bit 0 at address 000716) stops oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. The internal oscillator circuit of expansion function (Data acquisition / humming function) stops oscillation when expansion register XTAL_VCO, PDC_VCO_ON, VPS_VCO_ON = "L". Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) SI/O3,4 functions provided an external clock is selected. Table 2.5.2 shows the status of the ports in stop mode.Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to "1". When shifting from low-speed/ low power dissipation mode to stop mode, the value before stop mode is retained.
Table 2.5.2 Port status during stop mode Pin
_______ _______ _______
Memory expansion mode Retains status before wait mode "H " "H " "H " Retains status before wait mode Valid only in single-chip mode Valid only in single-chip mode
Single-chip mode
Address bus,data bus,CS0 to CS3, BHE
_____ ______ ________ ________
RD,WR,WRL,WRH
__________
HLDA,BCLK ALE Port CLKOUT When fC selected When f8,f32 selected
Retains status before wait mode "H " Retains status before wait mode
Rev. 1.0
35
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.5.5 Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However,peripheral function clock fC32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode,do not enter WAIT mode with this bit set to "1". Table 2.5.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. When using an interrupt to exit wait mode, make sure the interrupt used for that purpose is enabled and those not used for that purpose have their priority levels set to "0" before entering wait mode. When restored from wait mode by an interrupt, the microcomputer restarts operation from the interrupt routine using as BCLK the clock with which it was operating when the WAIT instruction was executed. When using a hardware reset or NMI interrupt only, be sure to set the priority levels of all other interrupts to 0 before entering wait mode.
Table 2.5.3 Port status during wait mode Pin
_______ _______ _______
Memory expansion mode Retains status before stop mode "H" "H" "H" Retains status before wait mode
Single-chip mode
Address bus, data bus, CS0 to CS3 BHE
_____ ______ ________ _________
RD, WR, WRL, WRH
________
HLDA, BCLK ALE Port CLKOUT When fc selected When f8, f32 selected
Retains status before wait mode Does not stop Does not stop when the WAIT peripheral function clock stop bit is "0". When the WAIT peripheral function clock stop bit is "1". the status immediately prior to entering wait mode is maintained.
Valid only in single-chip mode Valid only in single-chip mode
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.5.6 Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 2.5.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address 000616) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power dissipation mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. Table 2.5.4 Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 Invalid 1 0 Invalid Invalid 1 0 Invalid 1 0 Invalid Invalid 0 0 0 0 0 1 1 0 0 1 0 0 Invalid Invalid 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid 1 1 Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode
CM1i: bit i of address 000716 CM0i: bit i of address 000616
Rev. 1.0
37
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.5.7 Power control
The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode * High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. * Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock. * Low-speed mode fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock. * Low power dissipation mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. When in single-chip mode, the device can be operated with a low supply voltage (VCC = 3.0 V) only during low power dissipation mode. Before entering or exiting low power dissipation mode, always make sure the supply voltage VCC is 5 V. Note: When operating with a low supply voltage, be aware that only the CPU, ROM, RAM, input/ output ports, timers (timers A and B), and the interrupt control circuit can be used. All other internal resources (e.g., data slicer, DMAC, A/D, and D/A) cannot be used. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode The main clock and the sub-clock oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 2.5.5 is the state transition diagram of the above modes.
Rev. 1.0
38
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Transition of stop mode, wait mode Reset
Main clock is stopped Sub clock is stopped
CM10 = "1" WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt
CPU operation stopped
Stop mode
Interrupt
Medium-speed mode (divided-by-8 mode)
Wait mode
CPU operation stopped
Main clock is stopped Sub clock is stopped Interrupt
Stop mode
Main clock is stopped Sub clock is stopped
CM10 = "1"
High-speed/mediumspeed mode
Wait mode
CPU operation stopped
CM10 = "1"
Stop mode
Interrupt
Low-speed/low power dissipation mode
Wait mode
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode)
CM06 = "1" BCLK : f(XIN)/8 CM07 = "0" CM06 = "1" CM04 = "1" (Notes 1, 3) CM07 = "0" (Note 1) CM06 = "1" CM04 = "0"
Main clock is oscillating CM04 = "0" Sub clock is oscillating High-speed mode
BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0"
Medium-speed mode (divided-by-2 mode)
BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1"
Medium-speed mode (divided-by-8 mode)
BCLK : f(XIN)/8 CM07 = "0" CM06 = "1"
Main clock is oscillating Sub clock is oscillating Low-speed mode
CM07 = "0" (Note 1, 3) BCLK : f(XCIN) CM07 = "1" CM07 = "1" (Note 2)
Medium-speed mode (divided-by-4 mode)
BCLK : f(XIN)/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0"
Medium-speed mode (divided-by-16 mode)
BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1"
CM05 = "0" CM04 = "0"
CM05 = "1"
Main clock is oscillating Sub clock is stopped
CM04 = "1"
High-speed mode
BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" CM06 = "0" (Notes 1,3)
Medium-speed mode (divided-by-2 mode)
BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1"
Main clock is stopped Sub clock is oscillating Low power dissipation mode (Note 5)
CM07 = "1" (Note 2) CM05 = "1" BCLK : f(XCIN) CM07 = "1" CM07 = "0" (Note 1) CM06 = "0" (Note 3) CM04 = "1"
Medium-speed mode (divided-by-4 mode)
BCLK : f(XIN)/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0"
Medium-speed mode (divided-by-16 mode)
BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1"
Note 1: S witch clock after oscillation of main clock is sufficiently stable. Note 2: S witch clock after oscillation of sub clock is sufficiently stable. Note 3: C hange CM06 after changing CM17 and CM16. Note 4: T ransit in accordance with arrow. Note 5: The device can be operated with a low supply voltage (VCC = 3.0 V) in only low power dissipation mode. Always make sure the power supply voltage VCC is switched between 5.0 V and 3.0 V in this mode
Figure 2.5.5 State transition diagram of Power control mode
Rev. 1.0
39
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.6 Protection
The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 2.6.1 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (address 03F316) , SI/O3 control register (address 036216) and SI/O4 control register (address 036616) can only be changed when the respective bit in the protect register is set to "1". Therefore, important outputs can be allocated to port P9. If, after "1" (write-enabled) has been written to the port P9 direction register and SI/Oi control register (i=3,4) write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to "0" (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0".
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PRCR Bit symbol
PRC0
Address 000A16 Bit name
When reset XXXXX0002 Function RW
Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) Enables writing to port P9 direction register (address 03F316) and to 0 : Write-inhibited SI/Oi control register (i=3,4) 1 : Write-enabled (addresses 036216 and 036616)(Note)
PRC1
PRC2
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note: Writing a value to an address after "1" is written to this bit returns the bit to "0" . Other bits do not automatically return to "0" and they must therefore be reset by the program.
Figure 2.6.1 Protect register
Rev. 1.0
40
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.7 Interrupt 2.7.1 Interrupt
Figure 2.7.1 lists the types of interrupts.
Software
Interrupt
Special
Hardware
Peripheral I/O (Note)
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 2.7.1 Classification of interrupts
An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.
* Maskable interrupt :
Rev. 1.0
41

Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched
_______

MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.7.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are nonmaskable interrupts. * Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to "1". The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK interrupt A BRK interrupt occurs when executing the BRK instruction. * INT interrupt An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
Rev. 1.0
42
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.7.3 Hardware Interrupts
Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. * Reset ____________ Reset occurs if an "L" is input to the RESET pin. _______ * NMI interrupt _______ _______ An NMI interrupt occurs if an "L" is input to the NMI pin. ________ * DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. * Watchdog timer interrupt Generated by the watchdog timer. * Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed. * Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. For address match interrupt, see 2.7.10 Address match Interrupt. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. * Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. * DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. * Key-input interrupt ___ A key-input interrupt occurs if an "L" is input to the KI pin. * A-D conversion interrupt This is an interrupt that the A-D converter generates. * UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt These are interrupts that the serial I/O transmission generates. * UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt These are interrupts that the serial I/O reception generates. * Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates * Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates. ________ ________ * INT0 interrupt through INT5 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
Rev. 1.0
43
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.7.4 Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 2.7.2 shows the format for specifying the address. Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.
MSB
LSB Low address Mid address 0000 0000 High address 0000
Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3
Figure 2.7.2 Format for specifying interrupt vector addresses * Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 2.7.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 2.7.1 Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use
Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only.
Rev. 1.0
44
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
* Variable vector tables The addresses in the variable vector table can be modified, according to the user's settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 2.7.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 2.7.2 Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number Software interrupt number 0 Vector table address
Address (L) to address (H)
Interrupt source BRK instruction
Remarks Cannot be masked I flag
+0 to +3 (Note 1)
Software interrupt number 4 Software interrupt number 5 Software interrupt number 6 Software interrupt number 7 Software interrupt number 8 Software interrupt number 9 Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63
+16 to +19 (Note 1) +20 to +23 (Note 1) +24 to +27 (Note 1) +28 to +31 (Note 1) +32 to +35 (Note 1) +36 to +39 (Note 1) +40 to +43 (Note 1) +44 to +47 (Note 1) +48 to +51 (Note 1) +52 to +55 (Note 1) +56 to +59 (Note 1) +60 to +63 (Note 1) +64 to +67 (Note 1) +68 to +71 (Note 1) +72 to +75 (Note 1) +76 to +79 (Note 1) +80 to +83 (Note 1) +84 to +87 (Note 1) +88 to +91 (Note 1) +92 to +95 (Note 1) +96 to +99 (Note 1) +100 to +103 (Note 1) +104 to +107 (Note 1) +108 to +111 (Note 1) +112 to +115 (Note 1) +116 to +119 (Note 1) +120 to +123 (Note 1) +124 to +127 (Note 1) +128 to +131 (Note 1) to +252 to +255 (Note 1)
INT3 Timer B5 Timer B4 Timer B3 SI/O4/INT5 SI/O3/INT4 (Note 2) (Note 2)
Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit/NACK (Note 3) UART2 receive/ACK (Note 3) UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 INT0 INT1 INT2
Software interrupt
Cannot be masked I flag
Note 1: Address relative to address in interrupt table register (INTB). Note 2: It is selected by interrupt request cause bit (bit 6, 7 in address 035F16 ). Note 3: When IIC mode is selected, NACK and ACK interrupts are selected.
Rev. 1.0
45
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.7.5 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 2.7.3 shows the memory map of the interrupt control registers.
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Interrupt control register
Symbol TBiIC(i=3 to 5) BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) Address 004516 to 004716 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002
b7
b6
b5
b4
b3
b2
b1
b0
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
R
W
ILVL1
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol Address INTiIC(i=3) 004416 SiIC/INTjIC (i=4, 3) 004816, 004916 (j=5, 4) INTiIC(i=0 to 2) 005D16 to 005F16
When reset XX00X0002 XX00X0002 XX00X0002
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to "0"
R
W
ILVL1
ILVL2
IR
Interrupt request bit
(Note 1)
POL
Polarity select bit
Reserved bit Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
Figure 2.7.3 Interrupt control registers
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset. (2) Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). (3) Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt. Table 2.7.3 shows the settings of interrupt priority levels and Table 2.7.4 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted: * interrupt enable flag (I flag) = 1 * interrupt request bit = 1 * interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 2.7.3 Settings of interrupt priority levels
Interrupt priority level select bit
b2 b1 b0
Table 2.7.4 Interrupt levels enabled according to the contents of the IPL
IPL
IPL2 IPL1 IPL0
Interrupt priority level
Priority order
Enabled interrupt priority levels
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(4) Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.7.6 Interrupt Sequence
An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (a) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. (b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (d) Saves the content of the temporary register (Note) within the CPU in the stack area. (e) Saves the content of the program counter (PC) in the stack area. ( f) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. (1) Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 2.7.4 shows the interrupt response time.
Interrupt request generated Interrupt request acknowledged Time
Instruction (a)
Interrupt sequence (b)
Instruction in interrupt routine
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed.
Figure 2.7.4 Interrupt response time
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 2.7.5 Table 2.7.5 Time required for executing the interrupt sequence
Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd
________
16-Bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1)
8-Bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1)
Notes 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Notes 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK Address bus Data bus R W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Address 0000
Interrupt information
Indeterminate Indeterminate Indeterminate
SP-2 SP-2 contents
SP-4 SP-4 contents
vec vec contents
vec+2 vec+2 contents
PC
Figure 2.7.5 Time required for executing the interrupt sequence
(2) Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 2.7.6 is set in the IPL.
Table 2.7.6 Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
_______
Value set in the IPL 7 0 Not changed
Watchdog timer, NMI
Reset
Other
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 2.7.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address MSB
Stack area LSB
Address MSB
Stack area LSB [SP] New stack pointer value
m-4 m-3 m-2 m-1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs
m-4 m-3 m-2 m-1 m m+1
Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH)
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Figure 2.7.6 State of stack before and after acceptance of interrupt request
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 2.7.7 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
(1) Stack pointer (SP) contains even number
Address Stack area
(2) Stack pointer (SP) contains odd number
Address
Sequence in which order registers are saved
Stack area
Sequence in which order registers are saved
[SP] - 5 (Odd) [SP] - 4 (Even) [SP] - 3 (Odd) [SP] - 2 (Even) [SP] - 1(Odd) [SP] (Even) Program counter (PCL) Program counter (PCM) Flag register (FLGL)
[SP] - 5 (Even) [SP] - 4(Odd)
Program counter (PCL) Program counter (PCM) Flag register (FLGL)
(3) (4) (1) (2)
Finished saving registers in four operations.
(2) Saved simultaneously, all 16 bits
[SP] - 3 (Even) [SP] - 2(Odd)
Saved simultaneously, all 8 bits
Flag register Program (FLGH) counter (PCH)
(1) Saved simultaneously, all 16 bits
[SP] - 1 (Even) [SP] (Odd)
Program Flag register counter (PCH) (FLGH)
Finished saving registers in two operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 2.7.7 Operation of saving registers
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(4) Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. (5) Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 2.7.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.
_______
________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 2.7.8 Hardware interrupts priorities (6) Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 2.7.9 shows the circuit that judges the interrupt priority level.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Priority level of each interrupt
Level 0 (initial value)
INT1 Timer B2 Timer B0 Timer A3 Timer A1
Timer B4 INT3
High
INT2 INT0 Timer B1 Timer A4 Timer A2
Timer B3 Timer B5
UART1 reception UART0 reception UART2 reception/ACK A-D conversion DMA1 Bus collision detection
Serial I/O4/INT5
Priority of peripheral I/O interrupts (if priority levels are same)
Timer A0 UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt DMA0
Serial I/O3/INT4
Processor interrupt priority level (IPL)
Low
Interrupt request level judgment output to clock generating circuit (Fig.2.5.3)
Interrupt enable flag (I flag)
Address match
Interrupt request accepted
Watchdog timer
DBC
NMI
Reset
Figure 2.7.9 Maskable interrupts priorities (peripheral I/O interrupts)
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
______
2.7.7 INT Interrupt
________ ________
INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. ________ Of interrupt control registers, 004816 is used both as serial I/O4 and external interrupt INT5 input ________ control register, and 004916 is used both as serial I/O3 and as external interrupt INT4 input control register. Use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (035F16) - to specify which interrupt request cause to select. After having set an interrupt request cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt. Either of the interrupt control registers - 004816, 004916 - has the polarity-switching bit. Be sure to set this bit to "0" to select an serial I/O as the interrupt request cause. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register (035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register to `falling edge' ("0"). Figure 2.7.10 shows the Interrupt request cause select register.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR
Bit symbol
Address 035F16
When reset 0016
Bit name
INT0 interrupt polarity swiching bit INT1 interrupt polarity swiching bit INT2 interrupt polarity swiching bit INT3 interrupt polarity swiching bit INT4 interrupt polarity swiching bit INT5 interrupt polarity swiching bit Interrupt request cause select bit Interrupt request cause select bit
Fumction
0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : SIO3 1 : INT4 0 : SIO4 1 : INT5
RW
IFSR0 IFSR1 IFSR2 IFSR3 IFSR4 IFSR5 IFSR6 IFSR7
Figure 2.7.10 Interrupt request cause select register
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
______
2.7.8 NMI Interrupt
______ ______ ______
An NMI interrupt is generated when the input to the P85/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input.
2.7.9 Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as A-D input ports. Figure 2.7.11 shows the block diagram of the key input interrupt. Note that if an "L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt.
Port P104-P107 pull-up select bit
Pull-up transistor
Key input interrupt control register
Port P107 direction register
Port P107 direction register
(address 004D16)
P107/KI3
Pull-up transistor
Port P106 direction register
Interrupt control circuit
P106/KI2
Pull-up transistor
Key input interrupt request
Port P105 direction register
P105/KI1
Pull-up transistor
Port P104 direction register
P104/KI0
Figure 2.7.11 Block diagram of key input interrupt
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.7.10 Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot be used for external area. Figure 2.7.12 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW
AIER0 AIER1
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated.
Address match interrupt register i (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1
Address 001216 to 001016 001616 to 001416
When reset X0000016 X0000016
Function Address setting register for address match interrupt
Values that can be set R W 0000016 to FFFFF16
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated.
Figure 2.7.12 Address match interrupt-related registers
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.7.11 Precautions for Interrupts
(1) Reading address 0000016 * When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0". Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0". Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer * The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, gener_______ ating any interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ * As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pull-up) if unused. Be sure to work on it. _______ * The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ * Do not reset the CPU with the input to the NMI pin being in the "L" state. _______ * Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input _______ to the NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned down. _______ * Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input _______ to the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ * Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU. (4) External interrupt ________ * Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0 ________ through INT5 regardless of the CPU operation clock. ________ ________ * When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 2.7.13 shows the proce______ dure for changing the INT interrupt generate factor.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Clear the interrupt enable flag to "0" (Disable interrupt)
Set the interrupt priority level to level 0 (Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to "0"
Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to "1" (Enable interrupt)
Note:Execute the setting above individually.Don't execute two or more settings at once(by one instruction).
______
Figure 2.7.13 Switching condition of INT interrupt request (5) Rewrite the interrupt control register * To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
* When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.8 Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler. With XIN chosen for BCLK Watchdog timer period = pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = pre-scaler dividing ratio (2) X watchdog timer count (32768) BCLK
For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Figure 2.8.1 shows the block diagram of the watchdog timer. Figure 2.8.2 shows the watchdog timerrelated registers.
Prescaler
"CM07 = 0" "WDC7 = 0"
1/16
BCLK HOLD
1/128
"CM07 = 0" "WDC7 = 1"
Watchdog timer
Watchdog timer interrupt request
"CM07 = 1"
1/2
Write to the watchdog timer start register (address 000E16)
Set to "7FFF16"
RESET
Figure 2.8.1 Block diagram of watchdog timer
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC Bit symbol
Address 000F16 Bit name
When reset 000XXXXX2 Function RW
High-order bit of watchdog timer Reserved bit Reserved bit
WDC7
Must always be set to "0" Must always be set to "0" Prescaler select bit 0 : Divided by 16 1 : Divided by 128
Watchdog timer start register
b7 b0
Symbol WDTS
Address 000E16
When reset Indeterminate RW
Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written.
Figure 2.8.2 Watchdog timer control and start registers
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.9 DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 2.9.1 shows the block diagram of the DMAC. Table 2.9.1 shows the DMAC specifications. Figures 2.9.2 to 2.9.4 show the registers used by the DMAC.
Address bus
DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
(addresses 002916, 002816) DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003916, 003816) DMA1 transfer counter TCR1 (16)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 2.9.1 Block diagram of DMAC Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 2.9.1 DMAC specifications Item No. of channels Transfer memory space Specification 2 (cycle steal method) * From any address in the 1M bytes space to a fixed address * From a fixed address to any address in the 1M bytes space * From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________ ________ ________ ________
Maximum No. of bytes transferred DMA request factors (Note)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests Serial I/O3, 4 interrpt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode * Single transfer mode After the transfer counter underflows, the DMA enable bit turns to "0", and the DMAC turns inactive * Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a "0" is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to "1", the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive * When the DMA enable bit is set to "0", the DMAC is inactive. * After the transfer counter underflows in single transfer mode At the time of starting data transfer immediately after turning the DMAC active, the Forward address pointer and value of one of source pointer and destination pointer - the one specified for the reload timing for transfer forward direction - is reloaded to the forward direction address pointer,and the value counter of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0". Reading the register Can be read at any time. However, when the DMA enable bit is "1", reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
DMA0 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0SL
Address 03B816
When reset 0016
Bit symbol
Bit name DMA request cause select bit
b3 b2 b1 b0
Function
0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit
R
W
DSEL0
DSEL1
DSEL2
DSEL3
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMS DSR
DMA request cause expansion bit Software DMA request bit
0 : Normal 1 : Expanded cause If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0")
Figure 2.9.2 DMAC register (1)
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
DMA1 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM1SL
Address 03BA16
When reset 0016
Bit symbol
Bit name DMA request cause select bit
b3 b2 b1 b0
Function
0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive
R
W
DSEL0
DSEL1
DSEL2
DSEL3
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMS DSR
DMA request cause expansion bit Software DMA request bit
0 : Normal 1 : Expanded cause If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0")
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMiCON(i=0,1)
Address 002C16, 003C16
When reset 00000X002
Bit symbol DMBIT DMASL DMAS DMAE DSD DAD
Bit name Transfer unit bit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) 0 : 16 bits 1 : 8 bits
Function
R
W
0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward
(Note 2)
Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously.
Figure 2.9.3 DMAC register (2)
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
DMAi source pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol SAR0 SAR1
Address 002216 to 002016 003216 to 003016 Transfer count specification
When reset Indeterminate Indeterminate
Function * Source pointer Stores the source address
RW
0000016 to FFFFF16
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMAi destination pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol DAR0 DAR1
Address 002616 to 002416 003616 to 003416 Transfer count specification
When reset Indeterminate Indeterminate RW
Function * Destination pointer Stores the destination address
0000016 to FFFFF16
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMAi transfer counter (i = 0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol TCR0 TCR1
Address 002916, 002816 003916, 003816
When reset Indeterminate Indeterminate RW
Function * Transfer counter Set a value one less than the transfer count
Transfer count specification 000016 to FFFF16
Figure 2.9.4 DMAC register (3)
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses and, the level of the BYTE pin. In memory expansion mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of BYTE pin level When transferring 16-bit data over an 8-bit data bus (BYTE pin = "H") in memory expansion mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are required for reading the data and two are required for writing the data. Also, in contrast to when the CPU accesses internal memory, when the DMAC accesses internal memory (internal RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin. (c) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 2.9.5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 2.9.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle.
Rev. 1.0
68
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) 8-bit transfers 16-bit transfers from even address and the source address is even.
BCLK Address bus RD signal WR signal Data bus
CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use
(2) 16-bit transfers and the source address is odd Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK Address bus RD signal WR signal Data bus
CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use
(3) One wait is inserted into the source read under the conditions in (1)
BCLK Address bus RD signal WR signal Data bus
CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use
(4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
BCLK Address bus RD signal WR signal Data bus
CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 2.9.5 Example of the transfer cycles for a source read
Rev. 1.0
69
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 2.9.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 2.9.2 No. of DMAC transfer cycles Single-chip mode Transfer unit Bus width 16-bit (BYTE= "L") 8-bit (BYTE = "H") 16-bit (BYTE = "L") 8-bit (BYTE = "H") Access address Even Odd Even Odd Even Odd Even Odd No. of read No. of write cycles cycles 1 1 1 1 - - - - 1 1 2 2 - - - - Memory expansion mode No. of read No. of write cycles cycles 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2
8-bit transfers (DMBIT= "1")
16-bit transfers (DMBIT= "0")
Coefficient j, k Internal memory Internal ROM/RAM Internal ROM/RAM No wait With wait 1 2 SFR area 2 External memory Separate bus Separate bus No wait With wait 1 2 Multiplex bus 3
Rev. 1.0
70
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.9.1 DMA enable bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit.
2.9.2 DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data transfer starts. In addition, it can be set to "0" by use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. Turning the DMA request bit to "1" due to an internal factor is timed to be effected immediately before the transfer starts. (2) External factors An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected.
Rev. 1.0
71
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Figure 2.9.6 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur.
BCLK DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit Obtainm ent of the bus right
Figure 2.9.6 An example of DMA transfer effected by external factors
Rev. 1.0
72
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.10 Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Figures 2.10.1 and 2.10.2 show the block diagram of timers.
Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1" 1/32 Reset fC32
* Timer mode * One-shot mode * PWM mode
Timer A0 interrupt TA0IN
Noise filter
Timer A0
* Event counter mode
* Timer mode * One-shot mode * PWM mode
Timer A1 interrupt Timer A1
TA1IN
Noise filter
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A2 interrupt TA2IN
Noise filter
Timer A2
* Event counter mode
* Timer mode * One-shot mode * PWM mode
Timer A3 interrupt TA3IN
Noise filter
Timer A3
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A4 interrupt TA4IN
Noise filter
Timer A4
* Event counter mode
Timer B2 overflow
Note 1: The TA0IN pin (P71) is shared with RxD2 and the TB5IN pin, so be careful.
Figure 2.10.1 Timer A block diagram
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Clock prescaler
XIN
f1
XCIN
Clock prescaler reset flag (bit 7 at address 038116) set to "1"
1/32
Reset
fC32
1/8
1/4
f8 f32
f1 f8 f32 fC32
Timer A
* Timer mode * Pulse width measuring mode
TB0IN
Noise filter
Timer B0 interrupt Timer B0
* Event counter mode
* Timer mode * Pulse width measuring mode
TB1IN
Noise filter
Timer B1 interrupt
Timer B1
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B2 interrupt
TB2IN
Noise filter
Timer B2
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B3 interrupt
TB3IN
Noise filter
Timer B3
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B4 interrupt
TB4IN
Noise filter
Timer B4
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B5 interrupt
TB5IN
Noise filter
Timer B5
* Event counter mode
Note 1: The TB5IN pin (P71) is shared with RxD2 and the TA0IN pin, so be careful.
Figure 2.10.2 Timer B block diagram
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.10.1 Timer A
Figure 2.10.3 shows the block diagram of timer A. Figures 2.10.4 to 2.10.6 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer over flow. * One-shot timer mode: The timer stops counting when the count reaches "000016". * Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source selection
f1 f8 f32 fC32
Polarity selection
TAiIN (i = 0 to 4)
* Timer * One shot * PWM * Timer (gate function) * Event counter
Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits
Counter (16) Clock selection
Up count/down count Always down count except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0
Count start flag
(Address 038016) Down count External trigger
TB2 overflow TAj overflow
(j = i - 1. Note, however, that j = 4 when i = 0)
Up/down flag
(Address 038416)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
TAiOUT
(i = 0 to 4)
Pulse output
Toggle flip-flop
Figure 2.10.3 Block diagram of timer A
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TAiMR(i=0 to 4)
Address When reset 039616 to 039A16 0016
Bit symbol
TMOD0
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode
RW
TMOD1
MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source select bit (Function varies with each operation mode)
Figure 2.10.4 Timer A-related registers (1)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Timer Ai register (Note 1)
(b15) b7 (b8) b0 b7 b0
Symbol TA0 TA1 TA2 TA3 TA4
Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Function * Timer mode Counts an internal count source
Values that can be set
RW
000016 to FFFF16
* Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow
* One-shot timer mode Counts a one shot width
* Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator * Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator
000016 to FFFF16 (Note 2,4)
000016 to FFFE16 (Note 3,4) 0016 ~ FE16 (high-order address) 0016 ~ FF16 (low-order address) (Note 3,4)
Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to "000016 ",the counter does not operate and the timer Ai interrupt request is not generated.When the pulse is set to output, the pulse does not output from the TAiOUT pin. Note 3: When the timer Ai register is set to "000016 ",the pulse width modulator does not operate and the output level of the TAiOUT pin remains "L " level,,therefore the timer Ai interrupt request is not generated.This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to "0016 ". Note 4: Use MOV instruction to write to this register. Note 5: In the case of using "Event counter mode" as "Free-Run type", the timer register contents may be unkown when counting begins.(Refer 3. Usage Precaution.)
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 0016
Bit symbol
TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name
Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function
0 : Stops counting 1 : Starts counting
RW
Up/down flag (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Address 038416
When reset 0016
Bit symbol
TA0UD TA1UD TA2UD TA3UD TA4UD
Bit name
Function
0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause
RW
Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag
TA2P TA3P TA4P
Timer A2 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled Timer A3 two-phase pulse signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to "0"
Note 1: Use MOV instruction to write to this register. Note 2: Set the TAiIN and TAiOUT pins correspondent port direction registers to "0 ".
Figure 2.10.5 Timer A-related registers (2)
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset 00X000002
Bit symbol
TA0OS TA1OS TA2OS TA3OS TA4OS
Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag
Function 1 : Timer start When read, the value is "0"
RW
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. TA0TGL TA0TGH
Timer A0 event/trigger select bit
b7 b6
0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to "0".
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
When reset 0016
Bit symbol
TA1TGL
Bit name Timer A1 event/trigger select bit
Function
b1 b0
RW
TA1TGH TA2TGL
0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected
b3 b2
Timer A2 event/trigger select bit
TA2TGH TA3TGL TA3TGH
0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected
b5 b4
Timer A3 event/trigger select bit
0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected
b7 b6
TA4TGL TA4TGH
Timer A4 event/trigger select bit
0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to "0".
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol
Bit name
Function
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
CPSR
Clock prescaler reset flag
0 : No effect 1 : Prescaler is reset (When read, the value is "0")
Figure 2.10.6 Timer A-related registers (3)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 2.10.1) Figure 2.10.7 shows the timer Ai mode register in timer mode. Table 2.10.1 Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer f1, f8, f32, fC32 * Down count * When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer Ai register * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function * Gate function Counting can be started and stopped by the TAiIN pin's input signal * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed Specification
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0
Address When reset 039616 to 039A16 0016 Bit name Function
b1 b0
RW
Operation mode select bit Pulse output function select bit
0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
b4 b3
MR1
Gate function select bit
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
MR2
1 0 : Timer counts only when TAiIN pin is held "L" (Note 3) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 3) 0 (Must always be fixed to "0" in timer mode) Count source select bit
b7 b6
MR3 TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be "0" or "1". Note 3: Set the corresponding port direction register to "0".
Figure 2.10.7 Timer Ai mode register in timer mode
Rev. 1.0
78
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a twophase external signal. Table 2.10.2 lists timer specifications when counting a single-phase external signal. Figure 2.10.8 shows the timer Ai mode register in event counter mode. Table 2.10.3 lists timer specifications when counting a two-phase external signal. Figure 2.10.9 shows the timer Ai mode register in event counter mode. Table 2.10.2 Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification * External signals input to TAiIN pin (effective edge can be selected by software) Count source * TB2 overflow, TAj overflow Count operation * Up count or down count can be selected by external signal or software * When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Each time the timer overflows or underflows, the TAiOUT pin's polarity is reversed Note: This does not apply when the free-run function is selected. Divide ratio
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol TAiMR(i = 0, 1) Bit symbol TMOD0 TMOD1 MR0
Address 039616, 039716
When reset 0016 Function RW
Bit name Operation mode select bit Pulse output function select bit
b1 b0
0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4)
MR1 MR2 MR3 TCK0 TCK1
Count polarity select bit (Note 3) Up/down switching cause select bit
0 (Must always be fixed to "0" in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type(Note 5)
Invalid in event counter mode Can be "0" or "1"
Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAiOUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0". Note 5: In the case of using "Event counter mode" as "Free-Run type", the timer register contents may be unkown when counting begins.(Refer 3. Usage Precaution.)
Figure 2.10.8 Timer Ai mode register in event counter mode
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 2.10.3 Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4)
Item Count source Count operation
Specification * Two-phase pulse signals input to TAiIN or TAiOUT pin * Up count or down count can be selected by two-phase pulse signal * When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note1) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input Two-phase pulse input Count value can be read out by reading timer A2, A3, or A4 register * When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter * When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) * Normal processing operation (Timer A2 and Timer A3) The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is "H"
Divide ratio Count start condition Count stop condition
Interrupt request generation timing
TAiIN pin function TAiOUT pin function Read from timer Write to timer
Select function(Note 2)
TAiOUT TAiIN (i=2,3)
Up count
Up count
Up count
Down count
Down count
Down count
* Multiply-by-4 processing operation (Timer A3 and Timer A4) If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges Count down all edges
TAiIN (i=3,4)
Count up all edges Count down all edges
Note 1: This does not apply when the free-run function is selected. Note 2: Timer A3 alone can be selected.Timer A2 is fixed to normal processing operation,and timer A4 is fixed to multiply-by-4 processing operation.
Rev. 1.0
80
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Timer Ai mode register (When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016
Bit symbol TMOD0 TMOD1 MR0
Bit name Operation mode select bit Pulse output function select bit
b1 b0
Function 0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TA iOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TA iOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TA iOUT pin's input signal (Note 4)
RW
MR1 MR2 MR3 TCK0 TCK1
Count polarity select bit (Note 3) Up/down switching cause select bit
0 (Must always be fixed to "0" in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type(Note 5)
Invalid in event counter mode Can be "0" or "1"
Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAi OUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0". Note 5: In the case of using "Event counter mode" as "Free-Run type", the timer register contents may be unkown when counting begins.(Refer 3. Usage Precaution.)
Timer Ai mode register (When using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
010001
Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016
Bit symbol
TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1
Bit name
Operation mode select bit
b1 b0
Function
0 1 : Event counter mode
RW
0 (Must always be "0" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing) 1 (Must always be "1" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing) Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type(Note 3) 0 : Normal processing operation 1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to "1". Also, always be sure to set the event/trigger select bit (address 038316) to "00". Note 3: In the case of using "Event counter mode" as "Free-Run type", the timer register contents may be unkown when counting begins.(Refer 3. Usage Precaution.)
Figure 2.10.9 Timer Ai mode register in event counter mode
Rev. 1.0
81
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) One-shot timer mode In this mode, the timer operates only once. (See Table 2.10.4) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 2.10.10 shows the timer Ai mode register in one-shot timer mode. Table 2.10.4 Timer specifications in one-shot timer mode Item Specification Count source Count operation f1, f8, f32, fC32 * The timer counts down * When the count reaches 000016, the timer stops counting after reloading a new count Divide ratio Count start condition * If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value * An external trigger is input * The timer overflows * The one-shot start flag is set (= 1) Count stop condition
Interrupt request generation timing
* A new count is reloaded after the count has reached 000016 * The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer Ai register is read, it indicates an indeterminate value * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time)
TAiIN pin function TAiOUT pin function Read from timer Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit
b1 b0
Function 1 0 : One-shot timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3)
RW
MR1 MR2
External trigger select bit (Note 2) Trigger select bit
0 : One-shot start flag is valid 1 : Selected by event/trigger select register
MR3 TCK0 TCK1
0 (Must always be "0" in one-shot timer mode) Count source select bit
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 3: Set the corresponding port direction register to "0".
Figure 2.10.10 Timer Ai mode register in one-shot timer mode
Rev. 1.0
82
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 2.10.5) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 2.10.11 shows the timer Ai mode register in pulse width modulation mode. Figure 2.10.12 shows the example of how a 16-bit pulse width modulator operates. Figure 2.10.13 shows the example of how an 8-bit pulse width modulator operates. Table 2.10.5 Timer specifications in pulse width modulation mode
Item
Count source Count operation
Specification
f1, f8, f32, fC32 * The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new count at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs when counting * High level width n / fi n : Set value * Cycle time (216-1) / fi fixed * High level width n (m+1) / fi n : values set to timer Ai register's high-order address * Cycle time (28-1) (m+1) / fi m : values set to timer Ai register's low-order address * External trigger is input * The timer overflows * The count start flag is set (= 1) * The count start flag is reset (= 0) PWM pulse goes "L" Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time)
16-bit PWM 8-bit PWM Count start condition
Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
11
1
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Address When reset 0016 039616 to 039A16 Function
b1 b0
Bit name Operation mode select bit 1 1 : PWM mode
RW
1 (Must always be "1" in PWM mode) External trigger select bit (Note 1) Trigger select bit
0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2)
0: Count start flag is valid 1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator
b7 b6
MR3
16/8-bit PWM mode select bit Count source select bit
TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 2: Set the corresponding port direction register to "0".
Figure 2.10.11 Timer Ai mode register in pulse width modulation mode
Rev. 1.0
83
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected
1 / fi X (2
16
- 1)
Count source
TAiIN pin input signal
"H" "L"
Trigger is not generated by this signal 1 / fi X n
PWM pulse output from TAiOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fi : Frequency of count source (f1, f8, f32, fC32) Cleared to "0" when interrupt request is accepted, or cleared by software Note: n = 000016 to FFFE16.
Figure 2.10.12 Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TA iIN pin input signal) is selected
1 / fi X (m + 1) X (2 8 - 1) Count source (Note1)
TA iIN pin input signal
"H" "L"
1 / fi X (m + 1) Underflow signal of 8-bit prescaler (Note2) "L"
"H"
1 / fi X (m + 1) X n PWM pulse output from TA iOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fi : Frequency of count source (f1, f8, f32, fC32)
Cleared to "0" when interrupt request is accepted, or cleaerd by software
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16.
Figure 2.10.13 Example of how an 8-bit pulse width modulator operates
Rev. 1.0
84
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.10.2 Timer B
Figure 2.10.14 shows the block diagram of timer B. Figures 2.10.15 and 2.10.16 show the timer Brelated registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer overflow. * Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width.
Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits
Clock source selection
f1 f8 f32 fC32
TBiIN (i = 0 to 5)
* Timer * Pulse period/pulse width measurement
Reload register (16)
* Event counter Polarity switching and edge pulse Count start flag (address 038016) Counter reset circuit Can be selected in only event counter mode TBj overflow (j = i - 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5
Counter (16)
Address 039116 039016 039316 039216 039516 039416 035116 035016 035316 035216 035516 035416
TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4
Figure 2.10.14 Block diagram of timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address TBiMR(i = 0 to 5) 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Inhibited
R
W
MR0 MR1 MR2
Function varies with each operation mode
(Note 1) (Note 2)
MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode)
Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 2.10.15 Timer B-related registers (1)
Rev. 1.0
85
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Timer Bi register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TB0 TB1 TB2 TB3 TB4 TB5
Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Values that can be set
Function
* Timer mode Counts the timer's period * Event counter mode Counts external pulses input or a timer overflow * Pulse period / pulse width measurement mode Measures a pulse period or width
RW
000016 to FFFF16
000016 to FFFF16
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name
Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function
0 : Stops counting 1 : Starts counting
RW
Timer B3, 4, 5 count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TBSR
Address 034016
When reset 000XXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
TB3S TB4S TB5S Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag 0 : Stops counting 1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0")
Figure 2.10.16 Timer B-related registers (2)
Rev. 1.0
86
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 2.10.6) Figure 2.10.17 shows the timer Bi mode register in timer mode. Table 2.10.6 Timer specifications in timer mode Item Count source Count operation f1, f8, f32, fC32 * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register * When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Specification
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode
R
W
Invalid in timer mode Can be "0" or "1" 0 (Fixed to "0" in timer mode ; i = 0, 3)
Nothing is assiigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
(Note 1) (Note 2)
MR3
Invalid in timer mode. In an attempt to write to this bit, write "0". The value, if read in timer mode, turns out to be indeterminate. Count source select bit
b7 b6
TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 2.10.17 Timer Bi mode register in timer mode
Rev. 1.0
87
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 2.10.7) Figure 2.10.18 shows the timer Bi mode register in event counter mode. Table 2.10.7 Timer specifications in event counter mode Item Specification Count source * External signals input to TBiIN pin * Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio Count start condition Count stop condition 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows TBiIN pin function Count source input Read from timer Write to timer Count value can be read out by reading timer Bi register * When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode select bit
b1 b0
Function
0 1 : Event counter mode
b3 b2
R
W
Count polarity select bit (Note 1)
MR1
0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited
(Note 2)
MR2
0 (Fixed to "0" in event counter mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Invalid in event counter mode. In an attempt to write to this bit, write "0". The value, if read in event counter mode, turns out to be indeterminate. Invalid in event counter mode. Can be "0" or "1". Event clock select 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow
(j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3)
(Note 3)
MR3
TCK0 TCK1
Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be "0" or "1". Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding port direction register to "0".
Figure 2.10.18 Timer Bi mode register in event counter mode
Rev. 1.0
88
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 2.10.8) Figure 2.10.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 2.10.20 shows the operation timing when measuring a pulse period. Figure 2.10.21 shows the operation timing when measuring a pulse width. Table 2.10.8 Timer specifications in pulse period/pulse width measurement mode Item Specification Count source Count operation f1, f8, f32, fC32 * Up count * Counter value "000016" is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing * When measurement pulse's effective edge is input (Note 1) * When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to "1". The timer Bi overflow flag changes to "0" when the count start flag is "1" and a value is written to the timer Bi mode register.) TBiIN pin function Read from timer Measurement pulse input When timer Bi register is read, it indicates the reload register's content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode select bit Measurement mode select bit
b1 b0
Function
1 0 : Pulse period / pulse width measurement mode
b3 b2
R
W
MR1
0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Inhibited
MR2
0 (Fixed to "0" in pulse period/pulse width measurement mode; i = 0, 3)
(Note 2)
Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. MR3 TCK0 TCK1 Timer Bi overflow flag ( Note 1) Count source select bit 0 : Timer did not overflow 1 : Timer has overflowed
b7 b6
(Note 3)
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: It is Indeterminate when reset. The timer Bi overflow flag changes to "0" when the count start flag is "1" and a value is written to the timer Bi mode register. This flag cannot be set to "1" by software. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5.
Figure 2.10.19 Timer Bi mode register in pulse period/pulse width measurement mode
Rev. 1.0
89
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
"H" "L" Transfer (indeterminate value) Transfer (measured value)
Reload register transfer timing
counter (Note 1) (Note 1) (Note 2)
Timing at which counter reaches "000016" Count start flag
"1" "0"
Timer Bi interrupt request bit
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
"1" "0"
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 2.10.20 Operation timing when measuring a pulse period
Count source
Measurement pulse
"H" "L"
Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value)
Reload register transfer timing
counter
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Timing at which counter reaches "000016"
"1" "0"
Count start flag
Timer Bi interrupt request bit
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
"1" "0"
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 2.10.21 Operation timing when measuring a pulse width
Rev. 1.0
90
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.11 Serial I/O
Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4.
2.11.1 UART0 to 2
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 2.11.1 shows the block diagram of UART0, UART1 and UART2. Figures 2.11.2 and 2.11.3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table 2.11.1 shows the comparison of functions of UART0 through UART2, and Figures 2.11.4 to 2.11.8 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table 2.11.1 Comparison of functions of UART0 through UART2
Function CLK polarity selection
UART0 UART1
UART2
Possible Possible Possible
Impossible
(Note 1) (Note 1) (Note 1)
Possible Possible Possible Possible Impossible
(Note 1) (Note 1) (Note 1) (Note 1)
Possible Possible Possible
Impossible
(Note 1) (Note 2) (Note 1)
LSB first / MSB first selection
Continuous receive mode selection
Transfer clock output from multiple pins selection
Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch
Impossible
Possible (Note 3)
Impossible Possible
(Note 4)
Possible
Impossible
(Note 3)
Possible
Impossible
TxD, RxD port output format
CMOS output
CMOS output
N-channel open-drain output
Parity error signal output Bus collision detection
Impossible Impossible
Impossible Impossible
Possible
Possible
(Note 4)
Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface.
Rev. 1.0
91
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(UART0)
RxD0
UART reception
TxD0
1/16
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A116)
Clock synchronous type
1/16
Reception control circuit
Receive clock
Transmit/ receive unit
1 / (n0+1)
External
UART transmission
Clock synchronous type
Transmission control circuit
Transmit clock
Clock synchronous type
1/2
(when internal clock is selected)
Clock synchronous type (when internal clock is selected)
CLK0
CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected
Clock synchronous type (when external clock is selected)
CTS0 / RTS0
Vcc CTS/RTS disabled
RTS0
CTS0
(UART1)
RxD1
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A916)
1/16
TxD1
UART reception Reception control circuit Receive clock Transmit/ receive unit
Clock synchronous type UART transmission
1/16
1 / (n1+1)
External
Clock synchronous type Clock synchronous type
1/2 (when internal clock is selected)
Transmission control circuit
Transmit clock
CLK1
CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS disabled CTS/RTS selected Clock output pin select switch VCC CTS/RTS disabled
CTS1 / RTS1 / CLKS1
RTS1
CTS1
(UART2)
RxD2
RxD polarity reversing circuit
1/16
UART reception
Clock source selection f1 f8 f32 Bit rate generator Internal (address 037916)
Clock synchronous type UART transmission
1/16
Reception control circuit
Receive clock
TxD polarity reversing circuit Transmit/ receive unit
TxD2
1 / (n2+1)
External
Clock synchronous type Clock synchronous type
1/2
Transmission control circuit
Transmit clock
(when internal clock is selected)
CLK2
CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS selected
CTS/RTS disabled
CTS2 / RTS2
Vcc CTS/RTS disabled
RTS2
CTS2
n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2)
Figure 2.11.1 Block diagram of UARTi (i = 0 to 2)
Rev. 1.0
92
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Clock synchronous type UART (7 bits) UART (8 bits)
1SP
PAR disabled
Clock synchronous type
UART (7 bits)
UARTi receive register
RxDi
SP 2SP
SP
PAR
PAR enabled
UART
UART (9 bits)
Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16
UART (8 bits) UART (9 bits)
UART (9 bits)
Clock synchronous type
2SP SP SP 1SP
PAR
PAR enabled
UART
TxDi
PAR disabled Clock synchronous type
UART (7 bits)
UART (7 bits) UART (8 bits) Clock synchronous type
UARTi transmit register
"0"
SP: Stop bit PAR: Parity bit
Figure 2.11.2 Block diagram of UARTi (i = 0, 1) transmit/receive unit
Rev. 1.0
93
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
No reverse
RxD2
RxD data reverse circuit
Reverse
Clock synchronous type
1SP SP 2SP SP
PAR
PAR disabled
Clock synchronous type
UART (7 bits) UART (8 bits)
UART(7 bits)
UART2 receive register
PAR enabled
UART
UART (9 bits)
Clock synchronous type
UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 receive buffer register Address 037E16 Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 transmit buffer register Address 037A16 Address 037B16
UART (8 bits) UART (9 bits)
PAR enabled
UART (9 bits) UART
Clock synchronous type
2SP SP SP 1SP
PAR
PAR disabled
Clock synchronous type
"0"
UART (7 bits) UART (8 bits)
Clock synchronous type
UART(7 bits)
UART2 transmit register
Error signal output disable
No reverse
Error signal output circuit
Error signal output enable Reverse
TxD data reverse circuit
TxD2
SP: Stop bit PAR: Parity bit
Figure 2.11.3 Block diagram of UART2 transmit/receive unit
Rev. 1.0
94
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
UARTi transmit buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB U2TB
Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16
When reset Indeterminate Indeterminate Indeterminate Function RW
Transmit data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turn out to be indeterminate. Note: Use MOV instruction to write this register.
UARTi receive buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB U2RB
Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16
When reset Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Receive data
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". ABT OER FER PER SUM Arbitration lost detecting flag (Note 2) Overrun error flag (Note 1) 0 : Not detected 1 : Detected 0 : No overrun error 1 : Overrun error found Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid
Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0 16, 03A816 and 037816) are set to "0002" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03A6 16, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but "0" may be written. Nothing is assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value of this bit is "0".
UARTi bit rate generator
b7 b0
Symbol U0BRG U1BRG U2BRG
Address 03A116 03A916 037916 Function
When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW
Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Write a value to the register while transmit/receive stop. Note 2: Use MOV instruction to write to this register.
Figure 2.11.4 UARTi I/O-related registers (1)
Rev. 1.0
95
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name Serial I/O mode select bit
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set
1 0 0 : Transfer data 7 bits length 1 0 1 : Transfer data 8 bits length 1 1 0 : Transfer data 9 bits length 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit
0 : Internal clock 1 : External clock (Note) Invalid
Odd/even parity select bit Invalid
PRYE SLEP
Parity enable bit Sleep select bit
Invalid Must always be "0"
Note: Set the corresponding direction register to "0".
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name Serial I/O mode select bit
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
0 0 0 : Serial I/O invalid 0 1 0 : (Note1) 0 1 1 : Must not be set 1 1 1 : Must not be set
1 0 0 : Transfer data 7 bits length 1 0 1 : Transfer data 8 bits length 1 1 0 : Transfer data 9 bits length 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set Must always be fixed to "0" 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to "0"
CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit
0 : Internal clock 1 : External clock (Note2) Invalid
Odd/even parity select bit Invalid
PRYE IOPOL
Parity enable bit TxD, RxD I/O polarity reverse bit
Invalid 0 : No reverse 1 : Reverse Usually set to "0"
Notes1: Bit 2 to bit 0 are set to "0102" when I2C mode is used. 2: Set the corresponding direction register to "0".
Figure 2.11.5 UARTil I/O-related registers (2)
Rev. 1.0
96
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC0(i=0,1)
Address 03A416, 03AC16
When reset 0816
Bit symbol CLK0 CLK1 CRS
Bit name BRG count source select bit
Function (During clock synchronous serial I/O mode)
b1 b0 b1 b0
Function (During UART mode) 0 0 1 1 0 1 0 1 : f1 is selected : f8 is selected : f32 is selected : Must not be set
RW
0 0 1 1
0 1 0 1
: f1 is selected : f8 is selected : f32 is selected : Must not be set
CTS/RTS function select bit Transmit register empty flag
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
TXEPT
0 : Data present in transmit 0 : Data present in transmit register register (during transmission) (during transmission) 1 : No data present in transmit 1 : No data present in transmit register (transmission register (transmission completed) completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output
CRD
CTS/RTS disable bit
NCH
Data output select bit
CKPOL
CLK polarity select bit
Must always be "0"
UFORM Transfer format select bit
0 : LSB first 1 : MSB first
Must always be "0"
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C0
Address 037C16
When reset 0816
Bit symbol CLK0 CLK1 CRS
Bit name BRG count source select bit 0 0 1 1
Function (During clock synchronous serial I/O mode)
b1 b0 b1 b0
Function (During UART mode) 0 0 1 1 0 1 0 1 : f1 is selected : f8 is selected : f32 is selected : Must not be set
RW
0 1 0 1
: f1 is selected : f8 is selected : f32 is selected : Must not be set
CTS/RTS function select bit Transmit register empty flag
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
TXEPT
0 : Data present in transmit 0 : Data present in transmit register register (during transmission) (during transmission) 1 : No data present in transmit 1 : No data present in transmit register (transmission register (transmission completed) completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : TXDi pin is CMOS output open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0: TXDi pin is CMOS output open-drain output
CRD
CTS/RTS disable bit
Nothing is assigned.
CKPOL
1: to be "0". 1 : TXDi pin is N-channel In an attempt to write to this bit, write "0". The value, if read, turns out TXDi pin is N-channel
CLK polarity select bit
Must always be "0"
UFORM Transfer format select bit (Note 3)
0 : LSB first 1 : MSB first
0 : LSB first 1 : MSB first
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 2.11.6 UARTi I/O-related registers (3)
Rev. 1.0
97
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC1(i=0,1)
Address 03A516,03AD16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RW
RE RI
Receive enable bit Receive complete flag
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C1
Address 037D16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must be fixed to "0"
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Invalid
RW
RE RI
Receive enable bit Receive complete flag
U2IRS UART2 transmit interrupt cause select bit
U2RRM UART2 continuous receive mode enable bit
U2LCH Data logic select bit U2ERE Error signal output enable bit
0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled
Figure 2.11.7 UARTi I/O-related registers (4)
Rev. 1.0
98
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Bit symbol U0IRS
Symbol UCON
Address 03B016
When reset X00000002 Function (During UART mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)
Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit
Function (During clock synchronous serial I/O mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
RW
U1IRS
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode
(CLK output is CLK1 only)
Invalid
U1RRM UART1 continuous receive mode enable bit
Invalid
CLKMD0 CLK/CLKS select bit 0
Invalid
CLKMD1 CLK/CLKS select bit 1 (Note)
Must always be "0"
1 : Transfer clock output from multiple pins function selected Reserved bit Must always be "0"
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: * UART1 internal/external clock select bit (bit 3 at address 03A816) = "0".
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR Bit symbol IICM ABC BBS LSYN
Address 037716
When reset 0016 Function (During UART mode) Must always be "0" Must always be "0" Must always be "0"
(Note 1)
Bit name I2C mode selection bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit SDA digital delay selection bit (Notes 2 and 3)
Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I 2C mode 0 : Update per bit 1 : Update per byte
0 : STOP condition detected 1 : START condition detected
RW
0 : Disabled 1 : Enabled Must always be "0"
Must always be "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxD2 Must always be "0"
ABSCS
ACSE
Must always be "0"
SSS
Must always be "0"
0 : Analog delay output selection 1 : Digital delay output selection
SDDS
Notes 1: Nothing but "0" may be written. 2: Do not write "1" except at I 2C mode. Must always be "0" at normal mode. Bit 7 to bit5 (DL2 to DL0 = SDA digital delay value setting bit) of UART2 special mode register 3 (U2SMR3/address 037516) are initialized and become "000" when this bit is "0", analog delay circuit is selected. Reading and writing U2SMR3 are enablewhen SDDS = "0". 3: Delaying ; Only analog delay value when analog delay is selected, and only digital delay value when digital delay is selected.
Figure 2.11.8 UARTi I/O-related registers (5)
Rev. 1.0
99
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
UART2 special mode register 2 (I 2C bus exclusive register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR2
Address 037616
When reset 0016
Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI SHTC
Bit name I 2C mode selection bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit
Function Refer to Table 2.11.11 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output 0: Enabled 1: Disabled (high impedance) Set this bit to "1" in I2C mode (refer to Table 2.11.12)
RW
UART2 special mode register 3 (I 2C bus exclusive register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR3
Address 037516
When reset Indeterminate (initializing value is "0016" at SDDS = "1") Function (I2C bus exclusive)
Bit symbol
Bit name
RW
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be "0". "0" is read out when SDDS = 1. (Note1)
DL0
DL1 DL2
SDA digital delay value setting bit (Note1, Note2, Note3, Note4)
b7 b6 b5
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 : Analog delay 1 : 1-2 cycle of 1/f (Xin)(Digital delay) 0 : 2-3 cycle of 1/f (Xin)(Digital delay) 1 : 3-4 cycle of 1/f (Xin)(Digital delay) 0 : 4-5 cycle of 1/f (Xin)(Digital delay) 1 : 5-6 cycle of 1/f (Xin)(Digital delay) 0 : 6-7 cycle of 1/f (Xin)(Digital delay) 1 : 7-8 cycle of 1/f (Xin)(Digital delay)
Notes 1: Reading and writing is possible when bit7 (SDDS = SDA digital delay selection bit) of UART2 special mode register (U2SMR/address 037716) is "1". When set SDDS = "1" and read out initialized value of UART2 special mode register 3(U2SMR3), this value is "0016".When set SDDS = "1" and write to UART2 special mode register 3(U2SMR3), set "0" to bit 0 to bit 4. When SDDS = "0", writing is enable. When read out, this value is indeterminate. 2: When SDDS = "0" , this bit is initialized and become "000", selected analog delay circuit. This bit is become "000" after end reset released, and selected analog delay circuit. Reading out is possible when only SDDS = "1". when SDDS = "0", value which was read out is indeterminate. 3: Delaying ; Only analog delay value when analog delay is selected, and only digital delay value when digital delay is selected. 4: Delay level depends on SCL pin and SDA pin. And, when use external clock, delay is increase around 100ns. So test first, and use this.
Figure 2.11.9 UARTi -related registers (6)
Rev. 1.0
100
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.11.2 Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 2.11.2 and 2.11.3 list the specifications of the clock synchronous serial I/O mode. Figur 2.11.10 shows the UARTi transmit/receive mode register. Table 2.11.2 Specifications of clock synchronous serial I/O mode (1) Item Specification Transfer data format * Transfer data length: 8 bits Transfer clock * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0") : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "1") : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control * CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition * To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" _______ _______ _ When CTS function selected, CTS input level = "L" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" Reception start condition * To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" * When transmitting Interrupt request _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at generation timing address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change.
Rev. 1.0
101
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 2.11.3 Specifications of clock synchronous serial I/O mode (2) Item Select function * CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected * LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected * Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register * Transfer clock output from multiple pins selection (UART1) UART1 transfer clock can be chosen by software to be output from one of the two pins set * Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. * TxD, RxD I/O polarity reverse (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Specification
Rev. 1.0
102
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP
Address 03A016, 03A816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (See note 1)
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode 0 (Must always be "0" in clock synchronous serial I/O mode)
Note 1: Set a corresponding direction register to "0."
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol U2MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL
Address 037816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (See note 2)
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note1) 0 : No reverse 1 : Reverse
Notes 1: Usually set to "0". 2: Set a corresponding direction register to "0."
Figure 2.11.10 UARTi transmit/receive mode register in clock synchronous serial I/O mode
Rev. 1.0
103
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 2.11.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.) Table 2.11.4 Input/output pin functions in clock synchronous serial I/O mode
Pin name Function Method of selection (Outputs dummy data when performing reception only) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "1" Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) ="0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1" TxDi Serial data output (P63, P67, P70) Serial data input RxDi (P62, P66, P71) CLKi Transfer clock output (P61, P65, P72) Transfer clock input
CTSi/RTSi CTS input (P60, P64, P73)
RTS output Programmable I/O port
Rev. 1.0
104
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
* Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
"1" "0" "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" Data is set in UARTi transmit buffer register
Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi
"L"
TCLK
Stopped pulsing because CTS = "H"
Stopped pulsing because transfer enable bit = "0"
CLKi
TxDi Transmit register empty flag (TXEPT)
"1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transmit interrupt "1" request bit (IR) "0"
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity select bit = "0". * Transmit interrupt cause select bit = "0". Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi
* Example of receive timing (when external clock is selected)
"1" "0" "1" "0" "1" "0" "H"
Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
"L"
1 / fEXT
Receive data is taken in
CLKi
RxDi Receive complete "0" flag (Rl) Receive interrupt request bit (IR)
"1" "0" "1"
D0 D1 D2 D3 D4 D5 D6 D7
Transferred from UARTi receive register to UARTi receive buffer register
D0 D1 D2 D3 D4 D5
Read out from UARTi receive buffer register
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: Meet the following conditions are met when the CLK
Figure 2.11.11 Typical transmit/receive timings in clock synchronous serial I/O mode
Rev. 1.0
105
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) Polarity select function As shown in Figure 2.11.12 the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock.
* When CLK polarity select bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 1: The CLK pin level when not transferring data is "H".
* When CLK polarity select bit = "1"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 2: The CLK pin level when not transferring data is "L".
Figure 2.11.12 Polarity of transfer clock (2) LSB first/MSB first select function As shown in Figure 2.11.13, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".
* When transfer format select bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7
LSB first
D7
* When transfer format select bit = "1"
CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0
MSB first
D0
Note: This applies when the CLK polarity select bit = "0".
Figure 2.11.13 Transfer format
Rev. 1.0
106
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 2.11.14) The multiple pins function is valid only when the internal clock is selected for UART1.
Microcomputer
TXD1 (P67)
CLKS1 (P64) CLK1 (P65) IN CLK IN CLK
Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode.
Figure 2.11.14 The transfer clock output from the multiple pins function usage (4) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (5) Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = "1", and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 2.11.15 shows the example of serial data logic switch timing.
*When LSB first
Transfer clock TxD2
"H" "L" "H"
(no reverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
TxD2
"H"
(reverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
Figure 2.11.15 Serial data logic switch timing
Rev. 1.0
107
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.11.3 Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 2.11.5 and 2.11.6 list the specifications of the UART mode. Figure 2.11.16 shows the UARTi transmit/receive mode register. Table 2.11.5 Specifications of UART Mode (1) Item Specification Transfer data format * Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or nothing as selected * Stop bit: 1 bit or 2 bits as selected Transfer clock * When internal clock is selected (bit 3 at addresses 03A016 ,03A816 ,037816 = "0") : fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016 and 03A816 = "1") : fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)
_______ _______ _______ _______
Transmission/reception control * CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" _______ _______ - When CTS function selected, CTS input level = "L" Reception start condition * To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" - Start bit detection Interrupt request * When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change.
Rev. 1.0
108
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 2.11.6 Specifications of UART Mode (2) Item Select function Specification * Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers * Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. * TXD, RXD I/O polarity switch (UART2) This function is reversing TXD port output and RXD port input. All I/O data level is reversed.
Rev. 1.0
109
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits length 1 0 1 : Transfer data 8 bits length 1 1 0 : Transfer data 9 bits length 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
RW
Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit
PRYE SLEP
Note: Set a corresponding direction register to "0."
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits length 1 0 1 : Transfer data 8 bits length 1 1 0 : Transfer data 9 bits length Must always be fixed to "0" 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse
RW
Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note)
PRYE IOPOL
Note: Usually set to "0".
Figure 2.11.16 UARTi transmit/receive mode register in UART mode
Rev. 1.0
110
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 2.11.7 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.) Table 2.11.7 Input/output pin functions in UART mode
Pin name Function TxDi Serial data output (P63, P67, P70) RxDi Serial data input (P62, P66, P71) CLKi Programmable I/O port (P61, P65, P72) Transfer clock input Method of selection
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A016, 03A816) = "1" Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = "0" (Do not set external clock for UART2) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) ="0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1"
CTSi/RTSi CTS input (P60, P64, P73)
RTS output Programmable I/O port
Rev. 1.0
111
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
* Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L".
Data is set in UARTi transmit buffer register.
Transferred from UARTi transmit buffer register to UARTi transmit register
"H"
CTSi
"L"
Start bit TxDi
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
Parity bit
P
Stop bit
SP
Stopped pulsing because transmit enable bit = "0"
ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
* Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi
"1" Transmit register empty flag (TXEPT)
Stop bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
"0" "1" "0"
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Figure 2.11.17 Typical transmit timings in UART mode(UART0,UART1)
Rev. 1.0
112
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
* Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0" Data is set in UART2 transmit buffer register
Note
Transferred from UART2 transmit buffer register to UARTi transmit register Start bit Parity bit
P
TxD2
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7
"1" Transmit register empty flag (TXEPT) "0"
Transmit interrupt request bit (IR)
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Figure 2.11.18 Typical transmit timings in UART mode(UART2)
Rev. 1.0
113
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
* Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count source Receive enable bit RxDi "1" "0" Start bit Sampled "L" Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "H" "L" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software The above timing applies to the following settings : *Parity is disabled. *One stop bit. Transferred from UARTi receive register to UARTi receive buffer register
Stop bit
D0
D1
D7
Figure 2.11.19 Typical receive timing in UART mode (1) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0". (2) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 2.11.20 shows the example of timing for switching serial data logic.
* When LSB first, parity enabled, one stop bit
Transfer clock TxD2
(no reverse)
"H" "L" "H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TxD2
(reverse)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST : Start bit P : Even parity SP : Stop bit
Figure 2.11.20 Timing for switching serial data logic
Rev. 1.0
114
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use. (4) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 2.11.21 shows the example of detection timing of a buss collision (in UART mode).
Transfer clock
"H" "L"
TxD2
"H" "L"
ST
SP
RxD2 Bus collision detection interrupt request signal Bus collision detection interrupt request bit
"H" "L" "1" "0" "1" "0"
ST
SP
ST : Start bit SP : Stop bit
Figure 2.11.21 Detection timing of a bus collision (in UART mode)
Rev. 1.0
115
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.11.4 Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 2.11.8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Table 2.11.8 Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface) Item Specification Transfer data format * Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = "1012") * One stop bit (bit 4 of address 037816 = "0") * With the direct format chosen Set parity to "even" (bit 5 and bit 6 of address 037816 = "1" and "1" respectively) Set data logic to "direct" (bit 6 of address 037D16 = "0"). Set transfer format to LSB (bit 7 of address 037C16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and bit 6 of address 037816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 037D16 = "1") Set transfer format to MSB (bit 7 of address 037C16 = "1") Transfer clock * With the internal clock chosen (bit 3 of address 037816 = "0") : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 (Do not set external clock)
_______ _______
Transmission / reception control * Disable the CTS and RTS function (bit 4 of address 037C16 = "1") Other settings * The sleep mode select function is not available for UART2 * Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D16 = "1") Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = "1" - Transmit buffer empty flag (bit 1 of address 037D16) = "0" Reception start condition * To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = "1" - Detection of a start bit Interrupt request generation timing * When transmitting When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = "1") * When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an "L" level is output from the TXD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = "1") when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UART2 receive interrupt request bit does not change.
Rev. 1.0
116
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0" Data is set in UART2 transmit buffer register Note1
Transferred from UART2 transmit buffer register to UART2 transmit register Start bit Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2 RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
A "L" level returns from TxD 2 due to the occurrence of a parity error.
Signal conductor level (Note 2)
"1" Transmit register empty flag (TXEPT) "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine.
P
SP
The level is detected by the interrupt routine
Transmit interrupt request bit (IR)
"1" "0"
Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1".
Cleared to "0" when interrupt request is accepted, or cleared by software Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Tc
Transfer clock Receive enable bit (RE)
"1" "0"
Start bit
Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RxD2 TxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
A "L" level returns from TxD 2 due to the occurrence of a parity error.
Signal conductor level (Note 2) Receive complete flag (RI) Receive interrupt request bit (IR)
"1" "0" "1" "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Read to receive buffer
Read to receive buffer
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Figure 2.11.22 Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Rev. 1.0
117
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) Parity error signal output function If a parity error is detected when the error signal output enable bit (address 037D16, bit 7) has been set to "1", a low-level signal can be output from the TxD2 pin. Also, when operating in transmit mode, a transmit-complete interrupt is generated a half transfer clock cycle later than when the error signal output enable bit (address 037D16, bit 7) is set to "0". Therefore, a parity error signal can be detected in the transmit-complete interrupt program. Figure 2.11.23 shows the timing at which a parity error signal is output.
* LSB first
Transfer clock RxD2 TxD2 Receive complete flag
"H" "L" "H" "L" "H" "L" "1" "0"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
Hi-Z
ST : Start bit P : Even Parity SP : Stop bit
Figure 2.11.23 Output timing of the parity error signal (2) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 2.11.24 shows the SIM interface format.
Transfer clcck TxD2 (direct) TxD2 (inverse) D0 D1 D2 D3 D4 D5 D6 D7 P
D7
D6
D5
D4
D3
D2
D1
D0
P P : Even parity
Figure 2.11.24 SIM interface format
Rev. 1.0
118
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Figure 2.11.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up.
Microcomputer
SIM card TxD2 RxD2
Figure 2.11.25 Connecting the SIM interface
Rev. 1.0
119
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.11.5 UART2 Special Mode Register
The UART2 special mode register (address 037716) is used to control UART2 in various ways. Figure 2.11.26 shows the UART2 special mode register. Bit 0 of the UART special mode register (037716) is used as the I2C mode selection bit. Setting "1" in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus interface effective. Since this function uses clock-synchronous serial I/O mode, set this bit to "0" in UART mode.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR
Address 037716
When reset 0016
Bit symbol
IICM ABC BBS LSYN ABSCS
Bit name
I2 C mode selection bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit
SDA digital delay select bit (Notes 2 and 3)
Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I 2C mode 0 : Update per bit 1 : Update per byte
0 : STOP condition detected 1 : START condition detected
Function (During UART mode)
Must always be "0" Must always be "0"
RW
Must always be "0"
(Note 1)
0 : Disabled 1 : Enabled
Must always be "0"
Must always be "0"
0 : Rising edge of transfer clock 1 : Underflow signal of timer A0
0 : No auto clear function 1 : Auto clear at occurrence of bus collision
ACSE
Must always be "0"
SSS
SDDS
Must always be "0"
0 : Ordinary 1 : Falling edge of RxD2
Must always be "0"
0 : Selects analog delay output 1 : Selects digital delay output (Must always be "0" except at I 2C mode)
Notes 1: Nothing but "0" may be written. 2: Do not write "1" except at I 2C mode. Must always be "0" at normal mode. Bit 7 to bit5 (DL2 to DL0 = SDA digital delay value setting bit) of UART2 special mode register 3 (U2SMR3/address 0375 16) are initialized and become "000" when this bit is "0", analog delay circuit is selected. Reading and writing U2SMR are enable when SDDS = "0" . 3: Delaying ; Only analog delay value when analog delay is selected, and only digital delay value when digital delay is selected.
UART2 special mode register 3 (I 2C bus exclusive register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR3
Address 037516
When reset Indeterminate (initializing value is "00 16" at SDDS = "1")
Function (I2C bus exclusive)
Bit symbol
Bit name
RW
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be "0". "0" is read out when SDDS = 1. DL0 SDA digital delay value set bit
b7 b6 b5
DL1
DL2
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 : Selects analog delay 1 : 1-2 cycle of 1/f (Xin)(Digital delay) 0 : 2-3 cycle of 1/f (Xin)(Digital delay) 1 : 3-4 cycle of 1/f (Xin)(Digital delay) 0 : 4-5 cycle of 1/f (Xin)(Digital delay) 1 : 5-6 cycle of 1/f (Xin)(Digital delay) 0 : 6-7 cycle of 1/f (Xin)(Digital delay) 1 : 7-8 cycle of 1/f (Xin)(Digital delay)
Notes 1: Reading and writing is possible when bit7 (SDDS = SDA digital delay selection bit) of UART2 special mode register (U2SMR/address 0377 16) is "1". When set SDDS = "1" and read out initialized value of UART2 special mode register 3(U2SMR3), this value is "00 16".When set SDDS = "1" and write to UART2 special mode register 3(U2SMR3), set "0" to bit 0 to bit 4. When SDDS = "0", writing is enable. When read out, this value is indeterminate. 2: When SDDS = "0" , this bit is initialized and become "000", selected analog delay circuit. This bit is become "000" after end reset released, and selected analog delay circuit. Reading out is possible when only SDDS = "1". when SDDS = "0", value which was read out is indeterminate. 3: Delaying ; Only analog delay value when analog delay is selected, and only digital delay value when digital delay is selected. 4: Delay level depends on SCL pin and SDA pin. And, when use external clock, delay is increase around 100ns. So test first, and use this.
Figure 2.11.26 UART2 special mode register
Rev. 1.0
120
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
P70 through P72 conforming to the simplified I2C bus
P70/TXD2/SDA To DMA0, DMA1
Timer Selector
UART2 SDDS=0 or DL=000
Digital Delay (Divier)
IICM=1(SDDS=0) or DL=000(SDDS=1)
Analog
UART2
I/O
IICM=0 or IICM2=1 IICM=1 and IICM2=0
Transmission delay register IICM=0 or DL=000(SDDS=1) SDHI ALS
UART2 transmission/ NACK interrupt request
SDDS=1 and DL=000
D Noize Filter T
Q
Arbitration
IICM=1 Reception register IICM=0 UART2 IICM=1 and IICM2=0 IICM=0 or IICM2=1
To DMA0
UART2 reception/ACK interrupt request DMA1 request
Start condition detection
S R Q
Bus busy
NACK
Q T
Stop condition detection
Falling edge detection P71/RXD2/SCL I/O
R Q
L-synchronous output enabling bit
D
D
Q T
Data bus Internal clock
SWC2 CLK control
ACK
Selector
(Port P71 output data latch) UART2 IICM=1
9th pulse IICM=1
Bus collision/start, stop condition detection interrupt request
Noize Filter Noize Filter
IICM=1
Bus collision detection
UART2
IICM=0
External clock
IICM=0
Falling of 9th pulse SWC
Port reading
P72/CLK2 UART2 IICM=0 * With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register. I/O Timer
Selector
Figure 2.11.27 Functional block diagram for I2C mode Table 2.11.9 Features in I2C mode
Function 1 2 3 4 5 6 7 8 9 Factor of interrupt number 10 (Note 2) Factor of interrupt number 15 (Note 2) Factor of interrupt number 16 (Note 2) UART2 transmission output delay P70 at the time when UART2 is in use P71 at the time when UART2 is in use P72 at the time when UART2 is in use DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits Noise filter width Normal mode Bus collision detection UART2 transmission UART2 reception Not delayed TxD2 (output) RxD2 (input) CLK2 UART2 reception 15ns Reading the terminal when 0 is assigned to the direction register H level (when 0 is assigned to the CLK polarity select bit) I2C mode (Note 1) Start condition detection or stop condition detection No acknowledgment detection (NACK) Acknowledgment detection (ACK) Delayed(Digital / analog selection is possible) SDA (input/output) (Note 3) SCL (input/output) P72 Acknowledgment detection (ACK) 50ns Reading the terminal regardless of the value of the direction register The value set in latch P70 when the port is selected
10 Reading P71 11 Initial value of UART2 output
Note 1: Make the settings given below when I 2C mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Figure 2.11.27 hows the functional block diagram for I2C mode. Setting "1" in the I2C mode selection bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output, so the SDA output changes after SCL fully goes to "L". Can select analog delay or digital delay by SDA digital delay selection bit (7 bit of address 037716). When select digital delay, can select delay to 2 cycle to 8 cycle of f1 by UART2 special mode register 3 (address 037516) . Functions changed by I2C mode selection bit 2 is shown in below. Table 2.11.10 Delay circuit selection condition
Register value Contents IICM Digital delay selection 1 SDDS 1 1 Analog delay selection 1 0 No delay 0 0 (000) (000) DL 001 to 111 000 When select digital delay, analog delay is not added. Only digital delay. When select DL="000" , analog delay is chosen regardless of the value of SDDS. When SDDS="0" , DL is initialized and DL="000". Delay circuit is not selected when IICM="0". But, must set SDDS="0" when IICM="0".
An attempt to read Port P71 (SCL) results in getting the terminal's level regardless of the content of the port direction register. The initial value of SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The bus busy flag (bit 2 of the UART2 special mode register) is set to "1" by the start condition detection, and set to "0" by the stop condition detection. The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying "H" at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal's level is detected already went to "L" at the 9th transmission clock. Also, assigning 1101(UART2 reception) to the DMA1 request factor select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection. Bit 1 of the UART2 special mode register (037716) is used as the arbitration loss detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception buffer register (037F16, 037E16), and "1" is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to "1" and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to "1" goes the P71 data register to "0" in synchronization with the SCL terminal level going to "L".
Rev. 1.0
122
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Some other functions added are explained here. Figure 2.11.28 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to "0". If this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to "1" starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK TxD
Enabling transmission With "1: falling edge of RxD2" selected
CLK TxD RxD
Figure 2.11.28 Some other functions added
Rev. 1.0
123
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.11.6 UART2 Special Mode Register 2
UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure 2.11.29 shows the UART2 special mode register 2.
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR2
Address 037616
When reset 0016
Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI SHTC
Bit name I2 C mode selection bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit
Function Refer to Table 2.11.11 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output 0: Enabled 1: Disabled (high impedance) Set this bit to "1" in I2C mode (refer to Table 2.11.12)
RW
Figure 2.11.29 UART2 special mode register 2
Rev. 1.0
124
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode selection bit 2. Table 2.11.11 shows the types of control to be changed by I2C mode selection bit 2 when the I2C mode selection bit is set to "1". Table 2.11.12 shows the timing characteristics of detecting the start condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to "1" in I2C mode. Table 2.11.11 Functions changed by I2C mode selection bit 2
Function 1 Factor of interrupt number 15 2 Factor of interrupt number 16 IICM2 = 0 No acknowledgment detection (NACK) Acknowledgment detection (ACK) IICM2 = 1 UART2 transmission (the rising edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) The falling edge of the final bit of the reception clock The falling edge of the final bit of the reception clock
3 DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK) is assigned to the DMA request factor selection bits 4 Timing for transferring data from the UART2 reception shift register to the reception buffer. 5 Timing for generating a UART2 reception/ACK interrupt request The rising edge of the final bit of the reception clock The rising edge of the final bit of the reception clock
Table 2.11.12 Timing characteristics of detecting the start condition and the stop condition(Note1)
3 to 6 cycles < duration for setting-up (Note2) 3 to 6 cycles < duration for holding (Note2) Note 1 : When the start/stop condition count bit is "1" . Note 2 : "cycles" is in terms of the input oscillation frequency f(XIN) of the main clock. Duration for setting up
SCL SDA
Duration for holding
(Start condition)
SDA
(Stop condition)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
P70 through P72 conforming to the simplified I2C bus
P70/TxD2/SDA
Timer
I/O
Selector
UART2
SDDS=0 or DL=000
IICM=1 (SDDS=0) or DL=000 (SDDS=1) Analog delay IICM=0 or DL 000 (SDDS=1)
To DMA0, DMA1
UART2
Transmission register
IICM=0 or IICM2=1 IICM=1 and IICM2=0
UART2 transmission/ NACK interrupt request
Digital delay (Divider)
SDDS=1 and DL 000
SDHI ALS
DQ T Noize Filter
Arbitration To DMA0
IICM=1 Reception register IICM=0 UART2
IICM=1 and IICM2=0
S Q
Timer
IICM=0 or IICM2=1
UART2 reception/ACK interrupt request, DMA1 request
Start condition detection Stop condition detection
Falling edge detection P71/RxD2/SCL I/O
Q R R
Bus busy
NACK
D T D T Q
L-synchronous output enabling bit
Q
ACK
Data bus
Selector
UART2 IICM=1
Noize Filter Noize Filter
(Port P71 output data latch) Internal clock
SWC2
9th pulse IICM=1
Bus collision/start, stop condition detection interrupt request
IICM=1
Bus collision CLK control detection
UART2 Falling edge of 9 bit SWC
IICM=0
External clock
IICM=0
UART2
Port reading
* With IICM set to 1, the port terminal is to be readable
P72/CLK2
IICM=0
Selector
even if 1 is assigned to P7 1 of the direction register.
I/O
Timer
Figure 2.11.30 Functional block diagram for I2C mode Functions available in I2C mode are shown in Figure 2.11.30-- a functional block diagram. Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the instant when the arbitration loss detection flag is set to "1". Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit. With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this function, the UART2 transmission-reception clock becomes the logical product of the signal flowing through the internal SCL and that flowing through the SCL pin. This function operates over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock. Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to "1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to "0" frees the output fixed to "L".
Rev. 1.0
126
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit. Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows. (1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered next as the first bit. The UART2 output value, however, doesn't change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of the clock. Starting to transmit/receive signals to/from UART2 using this function doesn't change the value of the transmission buffer empty flag. To use this function, choose the external clock for the transfer clock. Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL pin wait output bit 2. Setting this bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin even if UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock is input/output. Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output enable bit. Setting this bit to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detection flag is turned on.
Rev. 1.0
127
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.11.7 S I/O3, 4
S I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os. Figure 2.11.31 shows the S I/O3, 4 block diagram, and Figure 2.11.32 shows the S I/O3, 4 control register.Table 2.11.13 shows the specifications of S I/O3, 4.
f1 f8 f32
SMi1 SMi0
Data bus
Synchronous circuit SMi3 SMi6 SMi6
1/2
1/(ni+1)
Transfer rate register (8) S I/O counter i (3)
P90/CLK3 (P95/CLK4)
SMi2 SMi3
S I/Oi interrupt request
P92/SOUT3 (P96/SOUT4) P91/SIN3 (P97/SIN4)
SMi5 LSB
MSB
S I/Oi transmission/reception register (8) 8
Note: i = 3, 4. ni = A value set in the S I/O transfer rate register i (036316, 036716).
Figure 2.11.31 S I/O3, 4 block diagram
Rev. 1.0
128
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SiC Bit symbol
SMi0 SMi1 SMi2 SMi3
Address 036216, 036616 Bit name
When reset 4016 Description
b1 b0
RW
In ternal synchronous clock select bit
0 0 : Selecting f 1 0 1 : Selecting f 8 1 0 : Selecting f 32 1 1 : Not to be used 0 : SOUTi output 1 : SOUTi output disable (high impedance) 0 : Input-output port 1 : SOUTi output, CLK function
SOUTi output disable bit S I/Oi port select bit (Note 2)
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be "0".
SMi5 SMi6 SMi7
Transfer direction lect bit Synchronous clock select bit (Note 2) SOUTi initial value set bit
0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock Effective when SMi3 = 0 0 : L output 1 : H output
Note 1: Set "1" in bit 2 of the protection register (000A 16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When using the port as an input/output port by setting the SI/Oi port select bit (i = 3, 4) to "1", be sure to set the sync clock select bit to "1".
SI/Oi bit rate generator (Note 1, Note 2)
b7 b0
Symbol S3BRG S4BRG
Address 036316 036716 Indeterminate
When reset Indeterminate Indeterminate Values that can be set 0016 to FF16 RW
Assuming that set value = n, BRGi divides the count source by n + 1
Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register.
SI/Oi transmit/receive register (Note)
b7 b0
Symbol S3TRR S4TRR
Address 036016 036416 Indeterminate
When reset Indeterminate Indeterminate RW
Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input.
Note: Write a value to this register while transmit/receive halts.
Figure 2.11.32 S I/O3, 4 related register
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
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Table 2.11.13 Specifications of S I/O3, 4 Item Transfer data format Transfer clock Specifications * Transfer data length: 8 bits * With the internal clock selected (bit 6 of 036216, 036616 = "1"): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (Note 1) * With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2) * To start transmit/reception, the following requirements must be met: - Select the synchronous clock (use bit 6 of 036216, 036616). Select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 036216, 036616). - SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1. - S I/Oi port select bit (bit 3 of 036216, 036616) = 1. - Select the transfer direction (use bit 5 of 036216, 036616) -Write transfer data to SI/Oi transmit/receive register (036016, 036416) * To use S I/Oi interrupts, the following requirements must be met: - Clear the SI/Oi interrupt request bit before writing transfer data to the SI/Oi transmit/receive register (bit 3 of 004916, 004816) = 0. * Rising edge of the last transfer clock. (Note 3) * LSB first or MSB first selection Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be selected. * Function for setting an SOUTi initial value selection When using an external clock for the transfer clock, the user can choose the SOUTi pin output level during a non-transfer time. For details on how to set, see Figure 2.11.33. * Unlike UART0-2, SI/Oi (i = 3, 4) is not divided for transfer register and buffer. Therefore, do not write the next transfer data to the SI/Oi transmit/receive register (addresses 036016, 036416) during a transfer. When the internal clock is selected for the transfer clock, SOUTi holds the last data for a 1/2 transfer clock period after it finished transferring and then goes to a high-impedance state. However, if the transfer data is written to the SI/Oi transmit/receive register (addresses 036016, 036416) during this time, SOUTi is placed in the high-impedance state immediately upon writing and the data hold time is thereby reduced.
Conditions for transmission/ reception start
Interrupt request generation timing Select function
Precaution
Note 1: n is a value from 0016 through FF16 set in the S I/Oi transfer rate register (i = 3, 4). Note 2: With the external clock selected: *Before data can be written to the SI/Oi transmit/receive register (addresses 036016, 036416), the CLKi pin input must be in the low state. Also, before rewriting the SI/Oi Control Register (addresses 036216, 036616)'s bit 7 (SOUTi initial value set bit), make sure the CLKi pin input is held low. * The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected, automatically stops. Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the "H" state.
Rev. 1.0
130
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) Functions for setting an SOUTi initial value When using an external clock for the transfer clock, the SOUTi pin output level during a non-transfer time can be set to the high or the low state. Figure 2.11.33 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) With "H" selected for SOUTi:
S I/Oi port select bit SMi3 = 0
Signal written to the S I/Oi transmission/reception register SOUTi's initial value set bit (SMi7)
SOUTi initial value select bit SMi7 = 1 (SOUTi: Internal "H" level)
S I/Oi port select bit (SMi3)
S I/Oi port select bit SMi3 = 0 1 (Port select: Normal port SOUTi)
D0 SOUTi (internal)
SOUTi terminal = "H" output
Port output SOUTi terminal output Initial value = "H" (Note) (i = 3, 4) Setting the SOUTi initial value to H Port selection (normal port SOUTi)
D0
Signal written to the S I/Oi register ="L" "H" "L" (Falling edge)
SOUTi terminal = Outputting stored data in the S I/Oi transmission/ reception register
Note: The set value is output only when the external clock has been selected. When initializing SOUTi, make sure the CLKi pin input is held "L" level. If the internal clock has been selected or if SOUT output disable has been set, this output goes to the high-impedance state.
Figure 2.11.33 Timing chart for setting SOUTi's initial value and how to set it (2) S I/Oi operation timing Figure 2.11.34 shows the S I/Oi operation timing
1.5 cycle (max) SI/Oi internal clock Transfer clock (Note 1) Signal written to the S I/Oi register S I/Oi output SOUTi
(i= 3, 4) "H" "L" "H" "L" "H" "L"
Note2
"H" "L" "H" "L" Hiz
D0
D1
D2
D3
D4
D5
D6
D7
Hiz
S I/Oi input SINi
(i= 3, 4)
SI/Oi interrupt request (i= 3, 4) bit
"1" "0"
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register. (i=3,4) (No frequency division, 8-division frequency, 32-division frequency.) Note 2: With the internal clock selected for the transfer clock, the SOUTi pin becomes to the high-impedance state after the transfer finishes. Note 3: Shown above is the case where the SOUTi (i = 3, 4) port select bit ="1".
Figure 22.11.34 S I/Oi operation timing chart
Rev. 1.0
131
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.12 A-D Converter
The A-D converter consists of one 8-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. Table 2.12.1 shows the performance of the A-D converter. Figure 2.12.1 shows the block diagram of the A-D converter, and Figures 2.12.2 and 2.12.3 show the A-D converter-related registers.
Table 2.12.1 Performance of A-D converter Performance Successive approximation (capacitive coupling amplifier) 0V to AVCC (VCC) fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) 8-bit q Without sample and hold function 3LSB q With sample and hold function 2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8 pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1) A-D conversion start condition q Software trigger A-D conversion starts when the A-D conversion start flag changes to "1" q External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is "1" and the __________ ADTRG/P97 input changes from "H" to "L" Conversion speed per pin q Without sample and hold function 49 AD cycles q With sample and hold function 28 AD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the AD frequency to 250kHZ min. With the sample and hold function, set the AD frequency to 1MHZ min. Item Method of A-D conversion Analog input voltage (Note 1) Operating clock AD (Note 2) Resolution Absolute precision
Rev. 1.0
132
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
CKS1=1
fAD 1/2 1/2
CKS0=1 CKS1=0
AD A-D conversion rate selection
CKS0=0
VREF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C016) (03C216) (03C416) (03C616) (03C816) (03CA16) (03CC16) (03CE16)
A-D register 0(8) A-D register 1(8) A-D register 2(8) A-D register 3(8) A-D register 4(8) A-D register 5(8) A-D register 6(8) A-D register 7(8) Vref Decoder
VIN
Comparator
Data bus
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111
OPA1, OPA0
OPA1,OPA0=0,0
OPA1,OPA0=1,1 OPA0=1
ANEX0
OPA1,OPA0=0,1
0 0 1 1
0 : Normal operation 1 : ANEX0 0 : ANEX1 1 : External op-amp mode
ANEX1
OPA1=1
Figure 2.12.1 Block diagram of A-D converter
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON0 Bit symbol
CH0 CH1
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH2 MD0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2)
0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started
(Note 2)
0 : fAD/4 is selected 1 : fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) When repeat sweep mode 1 is selected SCAN1
b1 b0
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 Must always be set to "0" 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected
b7 b6
MD2
Reserved bit CKS1 VCUT OPA0 OPA1 Frequency select bit 1 Vref connect bit External op-amp connection mode bit
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 2.12.2 A-D converter-related registers (1)
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
When reset
0000XXX02
000
Bit symbol
SMP Reserved bit
Bit name
A-D conversion method select bit
Function
0 : Without sample and hold 1 : With sample and hold Always set to "0"
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D register i
b7 b0
Symbol
ADi(i=0 to 7)
Address 03C016,03C216,03C416,03C616, 03C816,03CA16,03CC16,03CE16
When reset Indeterminate
Function
Eight bits of A-D conversion result
RW
Figure 2.12.3 A-D converter-related registers (2)
Rev. 1.0
135
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 2.12.2 shows the specifications of one-shot mode. Figure 2.12.4 shows the A-D control register in one-shot mode. Table 2.12.2 One-shot mode specifications Item Function Start condition Stop condition Specification The pin selected by the analog input pin select bit is used for one A-D conversion Writing "1" to A-D conversion start flag * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag End of A-D conversion One of AN0 to AN7, as selected Read A-D register corresponding to selected pin
Interrupt request generation timing Input pin Reading of result of A-D converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol ADCON0
Address 03D616
When reset 00000XXX2
Bit symbol
CH0
CH1
Bit name
Analog input pin select bit
b2 b1 b0
Function
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
RW
CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit
(Note 2) (Note 2)
0 0 : One-shot mode
0 : Software trigger 1 : ADTRG trigger A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started 0: fAD/4 is selected Frequency select bit 0 1: fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
1
00
Symbol ADCON1
Address 03D716
When reset 0016
Bit symbol
SCAN0 SCAN1 MD2
Bit name
A-D sweep pin select bit A-D operation mode select bit 1
Function
Invalid in one-shot mode
RW
0 : Any mode other than repeat sweep mode 1 Must always be set to "0".
Reserved bit CKS1 VCUT OPA0 OPA1 Frequency select bit1 Vref connect bit External op-amp connection mode bit
0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 2.12.4 A-D conversion register in one-shot mode
Rev. 1.0
136
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 2.12.3 shows the specifications of repeat mode. Figure 2.12.5 shows the A-D control register in repeat mode. Table 2.12.3 Repeat mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for repeated A-D conversion Star condition Writing "1" to A-D conversion start flag Stop condition Writing "0" to A-D conversion start flag Interrupt request generation timing None generated Input pin One of AN0 to AN7, as selected Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol ADCON0
Bit symbol
CH0 CH1
Address 03D616
Bit name
When reset 00000XXX2
Function
b2 b1 b0
RW
Analog input pin select bit
CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2) (Note 2)
0 1 : Repeat mode
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
1
00
Symbol ADCON1
Bit symbol
SCAN0 SCAN1 MD2
Reserved bit
Address 03D716
Bit name
When reset 0016
Function
RW
A-D sweep pin select bit Invalid in repeat mode
A-D operation mode select bit 1
0 : Any mode other than repeat sweep mode 1
Must always be set to "0".
CKS1 VCUT OPA0 OPA1
Frequency select bit 1 Vref connect bit External op-amp connection mode bit
0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 2.12.5 A-D conversion register in repeat mode
Rev. 1.0
137
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 2.12.4 shows the specifications of single sweep mode. Figure 2.12.6 shows the A-D control register in single sweep mode. Table 2.12.4 Single sweep mode specifications Item Function Start condition Stop condition Specification The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Writing "1" to A-D converter start flag * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag End of A-D conversion AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D register corresponding to selected pin
Interrupt request generation timing Input pin Reading of result of A-D converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function RW
Analog input pin select bit Invalid in single sweep mode
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Fbequency select bit 0
b4 b3
1 0 : Single sweep mode
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins)
RW
A-D sweep pin select bit
SCAN1 A-D operation mode select bit 1
MD2 Reserved bit CKS1 VCUT OPA0
0 : Any mode other than repeat sweep mode 1 Must always be set to "0".
Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2)
0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result isindeterminate. Note 2: Neither `01' nor `10' can be selected with the external op-amp connection mode bit.
Figure 2.12.6 A-D conversion register in single sweep mode
Rev. 1.0
138
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 2.12.5 shows the specifications of repeat sweep mode 0. Figure 2.12.7 shows the A-D control register in repeat sweep mode 0. Table 2.12.5 Repeat sweep mode 0 specifications Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0
Bit symbol
CH0
CH1 CH2
M D0 M D1
TR G
ADST
CKS0
Address 03D616
Bit name
When reset 00000XXX2
Function
RW
Analog input pin select bit Invalid in repeat sweep mode 0
A-D operation mode select bit 0
Trigger select bit
A-D conversion start flag
Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0
0 : Software trigger 1 : ADTRG trigger
0 : A-D conversion disabled 1 : A-D conversion started
0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
SCAN1
A-D operation mode select bit 1
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins)
M D2
Reserved bit
0 : Any mode other than repeat sweep mode 1
Must always be set to "0".
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected 1 : fAD is selected
VCUT OPA0
OPA1
Vref connect bit
External op-amp connection mode bit (Note 2)
1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither "01" nor "10" can be selected with the external op-amp connection mode bit.
Figure 2.12.7 A-D conversion register in repeat sweep mode 0
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 2.12.6 shows the specifications of repeat sweep mode 1. Figure 2.12.8 shows the A-D control register in repeat sweep mode 1. Table 2.12.6 Repeat sweep mode 1 specifications Item Function Specification All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Read A-D register corresponding to selected pin (at any time)
Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function RW
Analog input pin select bit Invalid in repeat sweep mode 1
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 1
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
01
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
A-D sweep pin select bit
When reset 0016 Function
When repeat sweep mode 1 is selected
b1 b0
RW
SCAN1 A-D operation mode select bit 1
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) 1 : Repeat sweep mode 1 Must always be set to "0". Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2) 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
MD2 Reserved bit CKS1 VCUT OPA0 OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither `01' nor `10' can be selected with the external op-amp connection mode bit.
Figure 2.12.8 A-D conversion register in repeat sweep mode 1
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 fAD cycle is achieved. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "0", input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is "0" and bit 7 is "1", input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A-D conversion. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "1", input via AN0 to AN7 is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 2.12.9 is an example of how to connect the pins in external operation amp mode.
Resistor ladder
Successive conversion register
Analog input
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
ANEX0
ANEX1
Comparator External op-amp
Figure 2.12.9 Example of external op-amp connection mode
Rev. 1.0
141
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.13 D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage Table 2.13.1 lists the performance of the D-A converter. Figure 2.13.1 shows the block diagram of the D-A converter. Figure 2.13.2 shows the D-A control register. Figure 2.13.3 shows the D-A converter equivalent circuit. Table 2.13.1 Performance of D-A converter Item Conversion method Resolution Analog output pin Performance R-2R method 8 bits 2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816) D-A0 output enable bit
R-2R resistor ladder
P93/DA0
D-A register1 (8)
(Address 03DA16) D-A1 output enable bit
R-2R resistor ladder
P94/DA1
Figure 2.13.1 Block diagram of D-A converter
Rev. 1.0
142
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DACON Bit symbol
DA0E DA1E
Address 03DC16 Bit name
D-A0 output enable bit D-A1 output enable bit
When reset 0016 Function
0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0"
D-A register
b7 b0
Symbol DAi (i = 0,1)
Address 03D816, 03DA16
When reset Indeterminate
Function
Output value of D-A conversion
RW RW
Figure 2.13.2 D-A control register
D-A0 output enable bit "0" DA0 "1" 2R MSB D-A0 register0 2R 2R 2R 2R 2R 2R 2R LSB R R R R R R R 2R
AVSS VREF
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 so that no current flows in the resistors Rs and 2Rs.
Figure 2.13.3 D-A converter equivalent circuit
Rev. 1.0
143
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.14 CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 2.14.1 shows the block diagram of the CRC circuit. Figure 2.14.2 shows the CRC-related registers. Figure 2.14.3 shows the calculation example using the CRC calculation circuit
Data bus high-order bits Data bus low-order bits
Eight low-order bits CRC data register (16)
Eight high-order bits (Addresses 03BD16, 03BC16)
CRC code generating circuit x16 + x12 + x5 + 1
CRC input register (8)
(Address 03BE16)
Figure 2.14.1 Block diagram of CRC circuit
CRC data register
(b15) b7 (b8) b0 b7 b0
Symbol CRCD
Address 03BD16, 03BC16
When reset Indeterminate Values that can be set
000016 to FFFF16
Function
CRC calculation result output register
RW
CRC input register
b7 b0
Symbo CRCIN Function
Data input register
Address 03BE16
When reset Indeterminate Values that can be set
0016 to FF16
RW
Figure 2.14.2 CRC-related registers
Rev. 1.0
144
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
b15
b0
(1) Setting 000016
CRC data register CRCD [03BD16, 03BC16]
b7
b0
(2) Setting 0116
CRC input register
CRCIN [03BE16]
2 cycles After CRC calculation is complete
b15 b0
118916
CRC data register
CRCD [03BD16, 03BC16]
Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 8 1 0000 0000 0000 0001 0001 1 0000 1 1000 0000 1000 0000 0 1 1000 MSB MSB Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1
9
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
(3) Setting 2316
CRC input register
CRCIN [03BE16]
After CRC calculation is complete
b15 b0
0A4116
CRC data register
CRCD [03BD16, 03BC16]
Stores CRC code
Figure 2.14.3 Calculation example using the CRC calculation circuit
Rev. 1.0
145
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.15 Expansion Function 2.15.1 Expansion function description
Expansion function cousists of data acquisition function and humming decoder function. Each function is controld by expansion memories. (1) Data acquisition function Corresponds to Hardware : TELETEXT, PDC, VPS, VBI and EPG-J Software : XDS, WSS and VBI-ID (2) Humming decoder function 8/4 humming and 24/18 humming
FSCIN
Clock generator
Vertical Syncseparate circuit
Clock generator
Clock generator
SYNCIN
Vertical Syncseparate circuit
Timing generator
Port control circuit
P11/SLICEON
CVIN1
Data slicer circuit
Serial/pararell conversion circuit
Expansion register
24/18 humming
8/4 humming
Slice RAM
Arbitrate circuit
Data bus (16bit)
CPU block
Figure 2.15.1 Block diagram of expansion function
Rev. 1.0
146
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.15.2 Expansion memory
Expansion function memory is divided by 2 patterns ; Slice RAM and expansion register. (Humming decoder operates by the register placed on SFR). Data writing and read out to the Slice RAM and the expansion register are carried out 16 bit unit by the data setting register (addresses 020E16, 021016, 021616 and 021816) placed on SFR. Contents of each memory and data setting register are shown in Table 2.15.1. Table 2.15.1 Expansion memory composition
Expansion memory Slice RAM Expansion register Store acquisition data. This register controls data acquisition Contents Data setting register Slice RAM address control register (020E16) Slice RAM data control register (021016) Expansion register address control register (021616) Expansion register data control register (021816)
Rev. 1.0
147
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.15.3 Slice RAM
Store 18-line slice data. There are 3 types of Slice data : PDC, VPS and VBI. All data are stored to addresses which corresponds to acquisition line (ex. 22 line' data is stored to addresses 20016 to 21716 ). 24 addresses (SR00x to SR17x) are prepared for 1 line, acquisition data is stored in order from LSB side. Then, acquisition datas and field information are stored to the top address of each line. Slice RAM composite is shown in Table 2.15.2. Table 2.15.2 Slice RAM composition
Slice RAM addresses SD15 SD14 SD13 SD12 SD11 SD10 (SA9 to SA0)
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Remarks
00016 00116
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 6th line or 318th line SR01F SR01E SR01D SR01C SR01B SR01A SR019 SR018 SR017 SR016 SR015 SR014 SR013 SR012 SR011 SR010 slice data
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
01616 01716 01816
SR16F SR16E SR16D SR16C SR16B SR16A SR169 SR168 SR167 SR166 SR165 SR164 SR163 SR162 SR161 SR160 SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
...
Unused area
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 7th line or 319th line
01F16 02016
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
slice data 8th line to 21th line or 320th line to 333 line slice data
03716 04016
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
...
1F716 20016
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 22th line or 334th line slice data
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
21716 22016
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
23716
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
For accessing to Slice RAM data, set accessing address (SA9 to SA0) (shown in Table 2.15.2) to Slice RAM address control register (address 020E16 ). Then read out data from Slice RAM data control register (address 021016 ). When end the data reading, Slice RAM address control register increments address automatically. Then, next address data reading is possible. Do not access to unused area of each character codes. Must set address to each line because unused area has no address' automatically increment. Slice RAM bit composition is shown in Figure 2.15.2, Slice RAM access registers are shown in Figure 2.15.3 and Slice RAM access block diagram is shown in Figure 2.15.4.
...
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170 SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 23th line or 335th line slice data
...
Rev. 1.0
148
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
The each head address of the address is corresponded to acquisition line has stored next acquisition information.
PDC VPS VBI Other
SR00F to SR004 0 0 0 0
SR003 field * (Note) field * (Note) field * (Note) 0
SR002 0 0 1 0
SR001 0 1 0 0
SR000 1 0 0 0
Note : * the first field : 1 the second field : 0
(1) PDC In case of the PDC data, 16 bits (2 data) are stored for the 1 address from the LSB side.
Clock run-in + flaming code Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 39 Data 40 Data 41 Data 42
L S B
SR010
ML SS BB
SR01F SR020
M S B
SR030 S02F
S03F
SR140
S14F SR150
S15F
SR16x to SR17x are unused area.
(2) VPS In case of the VPS data, 8 bits (a data) are stored for an address from the LSB side. Low-order 8 bits stores the acquisition data. And, high-order 8 bits become warning bit, when the send data is not recognized as bi-phase type. The case of bi-phase data ="1,0" or "0,1" (the bi-phase type) becomes "0" for this warning bit, and it becomes "1" in bi-phase data ="0,0" or "1,1" (it is not the bi-phase type). (For example, bi-phase data of SR011 is "0,0" or "1,1", "1" is set to SR019.)
Clock run-in + flaming code Data 1 Data 2 Data 3 Data 4 Data 11 Data 12 Data 13
L S B
SR010
ML SS BB
SR017 SR020
M S B
SR030 SR027 SR037 SR040
SR0B0 SR0B7SR0D0
SR0C0 SR0C7
SR0D7
SR047
SR0Ex to SR17x are unused area.
(3) VBI
Clock run-in + flaming code
Data 1
Data 2
Data 3
Data 4
Data 5
L S B
SR010
ML SS BB
SR017 SR020
M S B
SR030 SR027 SR037 SR040
SR050 SR047 SR057
SR06x to SR17x are unused area.
Figure 2.15.2 Slice RAM bit composition
Rev. 1.0
149
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Slice RAM address control register
b15 b9 b8 b7 b0
Symbol SA
Address 020E16
When reset 000016
Function Specify accessing Slice RAM address
Setting possible value R W 00016 to 23716
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated. Note : When access to Slice RAM, must be set Slice RAM at first, then use Slice RAM data control register (021016). Slice RAM address control register increments by accessing Slice RAM data control register. So, it is not neccesary to setting the next Slice RAM address.
Slice RAM data control register
b15 b9 b8 b7 b0
Symbol SD
Address 021016
When reset 000016
Function
Read out the data of Slice RAM. Read out data of Slice RAM which is specified by Slice RAM address control register (address 020E16) by reading this register.
RW
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.15.3 Slice RAM access registers
Data bus (16-bit)
(address 020E16)
Slice RAM address control register (10) (SA9 to SA0)
Slice RAM data control register (16) (SD15 to SD0)
(address 021016)
Increment automatically after data access
Slice RAM
Figure 2.15.4 Slice RAM access block diagram
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150
Rev. 1.0
DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SEKI0 Time base setting Display control setting _ Slicer control setting Sync separation, slice setting _ Acquisition setting _ _ _
_ PDC_HP4 VPS_HP4
DA5 to DA0
DD15 _ _ STBY0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ VPS_SUB _ SEKI1 Port setting _ _ _ _ _ _ _ Test setting _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SEKI2 _ _
_ PDC_HP5 VPS_HP5
DD14 _
DD13
DD12
DD11
Remarks
0016 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SEKI3 _ _
XTAL_VCO PDC_HP6 VPS_HP6
_
_
_
_
_
0116 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SLI_VP0 _ SEKI4 _ _
_ PDC_HP7 VPS_HP7
_
_
_
_
_
0216 TEST0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SEL_PDCH SLI_VP1 _ SEKI5 _ _
_ PDC_HP8 VPS_HP8
_
_
_
_
_
0316 _ _ _ _ _ _ _ _ _ _ _ PTC8 _ _ _ _ SLI_VP2 _ _ _ _
PDC_VCO_ON
_
_
_
TEST2
TEST1
0416 _ _ _ _ _ _ _ _ _ _ _ _ _ _ SLSLVL _ _ _ _ _
PDC_HP10 PDC_HP9 VPS_HP9 VPS_HP10
_
_
_
_
_
0516 _ _ _ _ _ _ _ _ _ _ _ ADON
_
_
_
_
_
_
0616 _ _ _ _ _ _ _ _ _ _
_
_
_
_
_
_
0716 _ _ _ _ _ _ _ _
SYNCSEP_ON0
_
_
_
_
_
0816
_
_
_
_
_
0916
_
_
_
_
_
0A16
_
_
_
_
_
0B16
_
PTD8
_
_
_
2.15.4 Expansion Register
0C16
_
_
_
TIMBAS
_
0D16
_
_
_
NXP
_
0E16
_
_
_
_
_
0F16
_
_
_
_
_
Table 2.15.3 Expansion register composition
1016 _ _ _ _ _ _ _ _ _ _ _ _ _ _ VBIF1
PDC_FLC4
_
_
_
_
_
1116 _ _ _ _
VPS_VCO_ON
_
_
_
_
_
1216 _ _ _ PD2 PD1 _ _ _ _ VBIF2
PDC_FLC5 PDC_FLC6
SEL_VPSH
_
_
_
_
1316
_
_
_
_
_
1416
_
_
_
_
_
_ _
PDC_HP3 VPS_HP3
_ Oscillation ON/OFF setting PDC slice position setting VPS slice position setting
1516
_
_
STBY1
_
_
1616 _ _
VPS_LINE2 VPS_LINE1 VPS_LINE0
_
_
_
_
_
1716 _ VPSF2
PDC_FLC3
HGSL
HGSLS
_
SOFTSLS
_
1816
_
_
_
_
_
_ VPSF1
PDC_FLC2
_ PDCF2
PDC_FLC1
_ PDCF1
_ Acquisition setting
PDC_FLC0 PDC, VPS flaming setting
1916
_
_
_
VPS_LINE4
VPS_LINE3
1A16 _ _ _ _ _ CHK_PDC
DIV_PDC2 DIV_VPS2 DIV_PDC3 DIV_VPS3 DIV_PDC4 DIV_VPS4 DIV_PDC5 DIV_VPS5 DIV_PDC6 DIV_VPS6 DIV_PDC7 DIV_VPS7
VPS_FLC7 VPS_FLC6 VPS_FLC5 VPS_FLC4 VPS_FLC3 VPS_FLC2 VPS_FLC1 VPS_FLC0 PDC_FLC7 _
1B16
_
_
_
CHK_VPS
_
_
DIV_PDC0
_
_
_
PDC, VPS flaming setting
DIV_PDCS2 DIV_PDCS1 DIV_PDCS0 PDC frequency setting
1C16
_
_
_
SELPEEK
DIV_PDC8
DIV_PDC1 DIV_VPS1
1D16 _ _ _ _ _ _ _ _ _ NGSYNC _ _ _ _ MIN0 _ _ _ MIN1 _ _ _ MIN2 _ _
_
_
_
_
DIV_VPS8
DIV_VPS0
DIV_VPSS2 DIV_VPSS1 DIV_VPSS0 VPS frequency setting
1E16
_
_
_
_
_
_ _ MAX5 _ _
_ FLD MAX4 _ _
_ _ MAX3 _ _
_ _ MAX2 _ _
_ _ MAX1 _ _
_ _ MAX0 _ _ Macro, field flag
_
1F16
_
_
_
_
_
2016
_
_
MIN5
MIN4
MIN3
Acquisition setting _ _
Control Data acquisition function. Expansion register composition is shown in Table 2.15.3.
2116
_
_
_
_
_
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
MITSUBISHI MICROCOMPUTERS
2216
_
_
_
_
_
151
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
For accessing to expantion register data, set accessing address (DA5 to DA0) (shown in Table 2.15.3) to expantion register address control register (address 021616). Then write data (DD15 to DD0) by expantion register data control register (address 021816). When end the data accessing, expantion register address control register increments address automatically. Then, next address data writing is possible. Expantion register access registers are shown in Figure 2.15.5, expansion register access block diagram is shown in Figure 2.15.6, and expansion register bit compositions are shown in p153 to 163.
Expansion register address control register
b15 b8 b7 b5 b0
Symbol DA
Address 021616
When reset 000016
Function Specify accessing expansion register address
Setting possible value 0016 to 2216
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated. Expansion register address auto increments set 0:vaid / 1:invaid (Note2) Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated. Note1 : When access to expansion register, must be set expansion register address at first, then use expansion register data control register (021816). Note2 : When bit 8 = "0" setting,expansion register data control register increments by accessing expansion register data control register,so it is not neccesary to setting the next expansion register address.When bit 8 = "1" setting, the address is fixed.
Expansion register data control register
b15 b8 b7 b0
Symbol DD
Address 021816
When reset 000016
Function
Write and read out the data of expansion register which is specified by expansion register address control register (address 021616)
Setting possible value 000016 to FFFF16
RW
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.15.5 Expansion register access registers composition
Data bus (16-bit)
(address 021616) (DA8)
Expansion register address control register (5) (DA5 to DA0)
Expansion register data control register (16) (DD15 to DD0)
(address 021816)
Increment automatically after data access
Expansion register
Figure 2.15.6 Expansion register access block diagram
Rev. 1.0
152
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Expansion register construction
(1) Address 0016 ( = DA5 to 0)
DD15 DD8DD7 DD0
0 0 00 0 00
00000000
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
STBY0
Stand-by mode selection bit
0 1
Normal mode Stand-by mode Must always be set to "0".
Reserved bit
(2) Addresses 0116, 0216 ( = DA5 to 0)
DD15 DD8DD7 DD0
0 0 00 0 00 0 00 0 00 0 00
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
(3) Address 0316 ( = DA5 to 0)
DD15 DD8DD7 DD0
000
0000000000
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
TEST0 TEST1 TEST2 Reserved bit Must always be set to "0". Test bit Must always be set to "0".
(4) Address 0416 to 0A16 ( = DA5 to 0)
DD15 DD8DD7 DD0
0 0 00 0 00 0 00 0 00 0 00
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
Rev. 1.0
153
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(5) Address 0B16 ( = DA5 to 0)
DD15 DD8DD7 DD0
0
00 0 00 0 0
000000
Bit symbol Reserved bit PTC8 Port P11 output selection bit 0 1 Bit name Function Must always be set to "0". P11 output SLICEON output Must always be set to "0".
RW
Reserved bit
0
PTD8 Port P11 data selection bit
1
Reserved bit
When port output : fixed to "L" when SLICEON output : specified negative polarity When port output : fixed to "H" when SLICEON output : specified positive polarity
Must always be set to "0".
(6) Address 0C16 ( = DA5 to 0)
DD15 DD8DD7 DD0
000
0 00 0 0 0 0 00 0 00
Bit symbol Reserved bit TIMBAS 0
Time base selection bit
Bit name
Function Must always be set to "0". Time base OFF Time base ON Must always be set to "0".
RW
1
Reserved bit
(7) Address 0D16 ( = DA5 to 0)
DD15 DD8DD7 DD0
000
0 00 0 0 0 0 00 0 00
Bit symbol Reserved bit NXP Broadcast method selection bit 0 1 Bit name Function Must always be set to "0". NTSC PAL Must always be set to "0".
RW
Reserved bit
(8) Address 0E16 ( = DA5 to 0)
DD15 DD8DD7 DD0
0 0 00 0 00 0 00 0 00 0 00
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
Rev. 1.0
154
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(9) Address 0F16 ( = DA5 to 0)
DD15 DD8DD7 DD0
0000000
00
00000
Bit symbol Reserved bit
0
Bit name
Function Must always be set to "0".
Do not set Generats PDC clock in based on FSCIN pin input signal.
RW
SEL_PDCH Reserved bit
PDC clock selection bit
1
Must always be set to "0". Data acquisition control bit 0 Data acquisition OFF 1 Data acquisition ON Must always be set to "0".
ADON Reserved bit
(10) Address 1016 ( = DA5 to 0)
DD15 DD8DD7 DD0
00000
00
01
0
Bit symbol Reserved bit
Flaming code check selection bit for VPS data.
Bit name
Function Must always be set to "0". 0 Later 8bits of flaming code 16bits
Former 4bits and later 4bits of flaming
RW
VPS_SUB
1 code 16bits (Select 8bits which is set in
VPS_FLC0 to 7)
Reserved bit Reserved bit SLI_VP0 SLI_VP1 SLI_VP2 SLSLVL
Acquisition start line selection bit (Field 1 and 2 are common) Stores data for 18 lines from the 6th line,normally. (SLI_VP2 to SLI_VPO = "316" fixed)
Must always be set to "1". Must always be set to "0".
If the acquisition start line is SLI_VS,

SLI_VS= 2nSLI_VPn+3 SLI_VS= 2nSLI_VPn+315
n=0 n=0 2
2
Stores data for 18 lines from line which is set by this register to slice RAM.
Acquisition level control bit
0 1
Auto level for data acquisition Fix level for data acquisition Must always be set to "0".
Reserved bit
SYNCSEP_ON0
Synchronous separation control bit
0 1
Sync-sep circuit OFF Sync-sep circuit ON Must always be set to "0".
Reserved bit
Rev. 1.0
155
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(11) Address 1116 ( = DA5 to 0)
DD15 DD8DD7 DD0
0100000000000000
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW

Reserved bit Reserved bit
Must always be set to "1". Must always be set to "0".
(12) Address 1216 ( = DA5 to 0)
DD15 DD8DD7 DD0
000000000
Bit symbol SEKI0 Bit name Data acquisition control bit 1
SEKI1
Function
SEKI0
N
RW
0 0 1 1
0 1 0 1
5 4 3 2
SEKI1
N times of the digital value after AD is done.
Data acquisition control bit 2 SEKI2
SEKI3
SEKI2
N
SEKI3
Not differentiate It is differentiated for digital value after the SEKI0, 1 operation at digital value in the before N/8 period(clock run-in period). SEKI5 SEKI4
N
0 0 1 1
0 1 0 1
4 3 1
SEKI4
Data acquisition control bit 3
0 0 1 1
0 1 0 1
4 3 1 Not differentiate
SEKI5
It is differentiated for digital value after the SEKI3, 2 operation at digital value in the after N/8 period(clock run-in period).
Reserved bit SEL_VPSH VPS clock selection bit
Must always be set to "0"
0 Do not set 1 input signal.
Generats VPS clock in based on FSCIN pin
(13) Addresses 1316, 1416 ( = DA5 to 0)
DD15 DD8DD7 DD0
0000000000000000
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
Rev. 1.0
156
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(14) Address 1516 ( = DA5 to 0)
DD15 DD8DD7 DD0
00
000
00
00
000
Bit symbol Reserved bit Synchronous clock oscillation 0 selection bit 1 Bit name Function Must always be set to "0". Synchronizing clock OFF Synchronizing clock oscillation Must always be set to "0". 0 1 PDC clock OFF PDC clock oscillation Must always be set to "0". VPS and VBI clock oscillation 0 selection bit 1 VPS and VBI clock OFF VPS and VBI clock oscillation Must always be set to "0". Stand-by mode selection bit 0 1 Reserved bit Normal mode Stand-by mode. Must always be set to "0".
RW
XTAL_VCO
Reserved bit
PDC_VCO_ON
PDC clock oscillation selection bit
Reserved bit
VPS_VCO_ON
Reserved bit STBY1
(15) Address 1616 ( = DA5 to 0)
DD15 DD8DD7 DD0
00000
0
Bit symbol PDC_HP3 PDC_HP4 PDC_HP5 PDC_HP6 PDC_HP7 PDC_HP8 Set to flaming code check start position PDC_HP9 PDC_HP10
Reserved bit Must always be set to "0". PDC, VPS, VBI clock phase control bit
Bit name PDC acquisition check start position selection bit
Function If the PDC acquisition check start position is PDC_HS,
10
RW
PDC_HS= T3 2(n-3)PDC_HPn
n=3
T3 : PDC clock run-in cycle /2
Set by the 144ns (1bit)
PD1 PD2
Adjust clock phase for Data slicer. Normaly, PD2 to PD1=(10)2 fixed.
Reserved bit
Must always be set to "0".
Rev. 1.0
157
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(16) Address 1716 ( = DA5 to 0)
DD15 DD8DD7 DD0
1
0
00
0
Bit symbol VPS_HP3 VPS_HP4 VPS_HP5 VPS_HP6 VPS_HP7 VPS_HP8 Set to flaming code check start position VPS_HP9 VPS_HP10 Reserved bit Nothing is assigned. Reserved bit 0 SOFTSLS Reserved bit 0 HGSLS HGSL Data slicer control bit 1 Slicer selection bit 1 Must always be set to "0". PDC, VPS, VBI XDS, WSS, VBI-ID Must always be set to "0". PDC, VPS VBI Must always be set to "1". Set by the 200ns (1bit)....VPS Set by the 800ns (1bit)....VBI Bit name VPS and VBI acquisition check start position selection bit Function If VPS and VBI acquisition check start position is VPS_HS,
10
RW
VPS_HS= T2 2(n-3)VPS_HPn
n=3
T2 : VPS or VBI clock run-in cycle /2
Must always be set to "0".
Data slicer control bit
(17) Address 1816 ( = DA5 to 0)
DD15 DD8DD7 DD0
0 0 00 0 00 0 00 0 00 0 00
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
Rev. 1.0
158
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(18) Address 1916 ( = DA5 to 0)
DD15 DD8DD7 DD0
000
00
Bit symbol PDCF1 PDCF2 VPSF1 VPSF2 VBIF1 VBIF2 Bit name PDC data acquisition selection 0 bit (field1) 1 PDC data acquisition selection 0 bit (field2) 1 VPS data acquisition selection 0 bit (field1) 1 VPS data acquisition selection 0 bit (field2) 1 VBI data acquisition selection bit (field1) VBI data acquisition selection bit (field2) 0 1 0 1 Function Do not acquisition field 1 PDC data Acquisition field 1 PDC data Do not acquisition field 2 PDC data Acquisition field 2 PDC data Do not acquisition field 1 VPS data Acquisition field 1 VPS data Do not acquisition field 2 VPS data Acquisition field 2 VPS data Do not acquisition field 1 VBI data Acquisition field 1 VBI data Do not acquisition field 2 VBI data Acquisition field 2 VBI data Must always be set to "0". When VPS data acquisition line is VPS_LINES, VPS_LINES = 2n VPS_LINEn + 7
n=0 4
RW
Reserved bit
VPSF_LINE0
VPS data acquisition line selection bit
VPSF_LINE1
VPSF_LINE2
Fixed to 16th line normally.)
(VPS_LINE4 to VPS LINE0 = "010012" fixed)
VPSF_LINE3
Setting value from 000002 to 100002 (7th line to 23 line)
VPSF_LINE4
Reserved bit
Must always be set to "0".
Rev. 1.0
159
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(19) Address 1A16 ( = DA5 to 0)
DD15 DD8DD7 DD0
Bit symbol PDC_FLC0 PDC_FLC1
Bit name Flaming code selection bit at PDC acquisition [PDC]
Function
Flaming code (8 bits) Clock run - in Data Setting
RW
PDC_FLC2
PDC_FLC0 to PDC_FLC7
PDC_FLC3 PDC_FLC4 PDC_FLC5 Flaming code selection bit at VBI acquisition [VBI]
PDC_FLC0 to 7 = 11100100
Clock run - in
Flaming code (24 bits)
Data
PDC_FLC6
PDC_FLC4 to 7
PDC_FLC7 VPS_FLC0 VPS_FLC1 VPS_FLC2 VPS_FLC3 VPS_FLC4 VPS_FLC5 Flaming code selection bit at VPS and VBI acquisition
VPS_FLC0 to 7 Set last 12bits
[VPS] When VPS_SUB (address1216) = 0
Flaming code (16 bits) Crock run - in Data
VPS_FLC0 to VPS_FLC7 Set last 8bits
VPS_FLC0 to 7 = 10011001 VPS_SUB = 1
Flaming code (16 bits)
Data
VPS_FLC6 VPS_FLC7
VPS_FLC0 to 3 VPS_FLC4 to 7 (Set first 4bits) (Set last 4 bits) = 8bits
VPS_FLC0 to 7 = 10001001
Rev. 1.0
160
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(20) Address 1B16 ( = DA5 to 0)
DD15 DD8DD7 DD0
00
0000000
00000
Bit symbol Reserved bit Flaming code check selection bit Bit name Function Must always be set to "0". 0 PDC_FLC5 valid 1 PDC_FLC5 invalid (Note1) Must always be set to "0". Flaming code check selection bit 0 VPS_FLC5 valid 1 VPS_FLC5 invalid (Note1) Must always be set to "0".
RW
CHK_PDC5 Reserved bit CHK_VPS5 Reserved bit

Note1. At VBI acquisition, must be set to "1".
(21) Address 1C16 ( = DA5 to 0)
DD15 DD8DD7 DD0
000
Bit symbol DIV_PDCS0 DIV_PDCS1 DIV_PDCS2 DIV_PDC0 DIV_PDC1 DIV_PDC2 DIV_PDC3 DIV_PDC4 DIV_PDC5 DIV_PDC6 DIV_PDC7 DIV_PDC8 SELPEEK Peek point detect selection bit 0 Detect from A/D data 1 Detect from data of digital calculation
after normally "1"setting.
Bit name PLL control bit for PDC
Function Contorl the acquisition clock frequency fPDC for PDC.
RW
DIV_PDC8 to DIV_PDC0 = (000010010)2 DIV_PDCS2 to DIV_PDCS0 = (101)2 PLL divided value selection bit for PDC
Reserved bit
Must always be set to "0".
Rev. 1.0
161
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(22) Address 1D16 ( = DA5 to 0)
DD15 DD8DD7 DD0
0000
Bit symbol DIV_VPSS0 DIV_VPSS1 DIV_VPSS2 DIV_VPS0 DIV_VPS1 DIV_VPS2 DIV_VPS3 DIV_VPS4 DIV_VPS5 DIV_VPS6 DIV_VPS7 DIV_VPS8 Reserved bit Must always be set to "0". PLL divided value selection bit for VPS and VBI Bit name PLL control bit for VPS and VBI Function Control the acquisition clock frequency fVPS for VPS and VBI. DIV_VPS8 to DIV_VPS0 = (000001111)2 DIV_VPSS2 to DIV_VPSS0 = (110)2
RW
(23) Address 1E16 ( = DA5 to 0)
DD15 DD8DD7 DD0
0 0 00 0 00 0 00 0 00 0 00
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
(24) Address 1F16 ( = DA5 to 0)
DD15 DD8DD7 DD0
Bit symbol Reserved bit
FLD Fild flag
Bit name
Function Writing is disable. Reading exclusive bit.
0 The secound field. 1 The first field. Writing is disable. Reading exclusive bit.
RW
Reserved bit
NGSYNC
synchronous signal detected flag (Note 1)
0 Normal 1 Abnormalities
Writing is disable. Reading exclusive bit.
Reserved bit
Note 1: This flag detects unwanted signals during the sync signal (slice period).
Rev. 1.0
162
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(25) Address 2016 ( = DA5 to 0)
DD15 DD8DD7 DD0
00
00
Bit symbol MAX0 MAX1 MAX2 MAX3 MAX4 MAX5 Reserved bit Must always be set to "0". Bit name Acquisition data sampling maximum value selection bit Function Set acquisition data sampling maximum value after A/D conversion. SAMAX = 2n MAXn (Note1)
n=0 5
RW
MIN0 MIN1 MIN2 MIN3 MIN4 MIN5
Acquisition data sampling minimum value selection bit
Set acquisition data sampling minimun value after A/D conversion. SAMIN = 2n MINn (Note1)
n=0 5
Reserved bit Note1.
Must always be set to "0".
Video signal
Sampling image after A/D conversion A/D conversion SAMAX maximun value
SAMIN Clock run in
A/D conversion minimum value
(26) Address 2116, 2216 ( = DA5 to 0)
DD15 DD8DD7 DD0
0 0 00 0 00 0 00 0 00 0 00
Bit symbol Reserved bit Bit name Function Must always be set to "0".
RW
Rev. 1.0
163
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.15.5 Expansion Register Construction Composition
(1) Acquisition timming The SLICEON signal is output in the acquisition possible period.
The first field
Vertical blanking erase period pulse Acquisition possible period
622 623 624 625 1
2
3
4
5
6
7
8
9
19
20
21
22
23
24
SLICEON output period
The second field
310 311 312 313 314 315 316 317 318 319 320 321
331 332 333 334 335 336
The scanning lines number in figure is corresponds to slice RAM .
Figure 2.15.7 Acquisition timing
Rev. 1.0
164
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.15.6 8/4 Humming Decoder
8/4 humming decoder opetates only by written the data which 8/4 humming- decoded to 8/4 humming register (address 021A16). 8/4 humming register consists of 16 bits, can decode two data at a time. Can obtain the decoded result by reading 8/4 humming register, and the decoded value and error information are output. Corrects and outputs the decoded value for single error, and outputs only error information for double error. Decoded result is shown in Figure 2.15.8 and humming 8/4 register composition is shown in Figure 2.15.9.
Humming data
MSB LSB MSB
Humming data
LSB
Writing Address
021A16 8/4 humming register
Reading
Error information 0 0 Error information 0 0 Decode value
MSB LSB
Decode value
MSB LSB
"1" output when single error "1" output when double error
"1" output when single error "1" output when double error
Figure 2.15.8 Decoded result
Humming 8/4 register
b15 b8 b7 b0
Symbol HM 8
Address 021A16
When reset 000016
Function
8/4 humming decoder opetates only by written the data which 8/4 humming-decoded to 8/4 humming register.Can obtain the decoded result by reading this register, and can decode 2 couples of data at the same time.
RW
Figure 2.15.9 Humming 8/4 register composition
Rev. 1.0
165
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.15.7 24/18Humming Decoder
24/18 humming decoder operates only by written the data which 24/18 humming-encoded to 24/18 humming register 0 (address 021C16) and 1 (address 021E16). Can obtain the decoded result by reading the same 24/18 humming register. Decoded result is shown in Figure 2.15.10 and humming 24/18 register composition is shown in Figure 2.15.11.
Humming data H
MSB
Humming data M
Humming data L
LSB
Writing Address 021E16 24/18 humming register 1
Writing 24/18 humming register 0 Reading
Decode value MSB
Address 021C16
Reading Error information
Decode value
LSB
0
0
0
0
0
0
0
0
0
0
0
0
"1" output when single error "1" output when double error
Output after correcting single error
Figure 2.15.10 Decoded result
Humming 24/18 register 0
b15 b8 b7 b0
Symbol HM0
Address 021C16
When reset 000016
Function
24/18 humming decoder opetates by two ways : writing data low-order and middle-order 16 bits to this register and writing data high-order 8 bits to humming 24/18 register 1 (021E16). Can obtain the decoded result by reading this register and humming 24/18 register 1.
RW
Humming 24/18 register 1
b15 b8 b7 b0
Symbol HM1
Address 021E16
When reset 000016
Function
24/18 humming decoder opetates by two ways : writing data low-order and middle-order 16 bits to humming 24/18 register 0 (021C16) to this register and writing data high-order 8 bits to this register. Can obtain the decoded result by reading this register and humming 24/18 register 0.
RW
Figure 2.15.11 Humming 24/18 register composition
Rev. 1.0
166
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Continuous error correction When uses humming 8/4 (address 021A16) at tha same time as humming 24/18, can do the continuous error correction. Continuous error correction sequence is shown in Figure 2.15.12.
A
Humming data M Humming data L Humming data H Humming data M Humming data L Humming data H
Humming data L Humming data H Humming data M Humming data L Humming data H Humming data M
B
C
D
E
1. Writes data A to address 021C16 and writes data B to address 021E16. (Setting the humming data and L of humming data .) 2. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ). 3. Writes data C to address 021A16 (Setting H and M of the humming data ). 4. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ). 5. Writes data D to address 021C16 and writes data E to 021E16 (Setting the humming data and L of humming data .) 6. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ). 7. Writes data F to address 021A16 (Setting H and M of the humming data ). 8. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ).
F
Figure 2.15.12 Continuous error correction sequence Then, because using a part of circuit of humming 8/4 about this operation, cannot use this operation at the same time. When using the humming circuit, do the decoded result reading operation at once after the setting data of humming. And do not access other memories (Including the humming circuit) before reading of the decoded result.
Rev. 1.0
167
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.15.8 I/O Composition of pins for Expansion Memory
Figure 2.15.13 and figure 2.15.14 show pins for expansion memory.
CVIN1
CVIN1
VCC
to slicer (Note 2)
VSS
SYNCIN
from internal circuit
to internal circuit
VDD2 VCC from internal circuit
input (Note 2)
VSS
to internal circuit
VSS2
P11/SLICEON
from internal circuit
VCC VCC
OUTPUT (Note 2)
VSS
Port P11 data selection bit (Note 1)
VSS
Port P11 output selection bit (Note 1)
Note1 : Refer expansion register construction Note2 : Expamsion register construction composition Do not apply a voltage higher than Vcc to each port.
Figure 2.15.13 Pins for expansion memory(1)
Rev. 1.0
168
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
VDD2
LP2, LP3, LP4
VCC
from internal circuit
(Note 1)
OUTPUT
VSS VSS2 to internal circuit
FSCIN
VCC
INPUT (Note 1)
to internal circuit
VSS VSS2
from internal circuit
SVREF
VCC
VDD2
from internal circuit
INPUT (Note 1)
VSS
to internal circuit
VSS2
Note1 :
Expamsion register construction composition Do not apply a voltage higher than Vcc to each port.
Figure 2.15.14 Pins for expansion memory(2)
Rev. 1.0
169
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
2.16 Programmable I/O Ports
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figures 2.16.1 to 2.16.4 show the programmable I/O ports. Figure 2.16.5 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 2.16.6 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. In memory expansion mode, the contents of corresponding ________ direction register of pins __________ ________ ________ _____ ________ ______ ________ ________ __________ A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Note: There is no direction register bit for P85.
(2) Port registers
Figure 2.16.7 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. In memory expansion mode, the contents of corresponding port register of pins A0 to ________ ________ _____ ________ ______ ________ ________ ________ __________ __________ A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified.
(3) Pull-up control registers
Figure 2.16.8 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. However, in memory expansion mode, the pull-up control register of P0 to P3, P40 to P43, and P5 is invalid. The contents of register can be changed, but the pull-up resistance is not connected.
(4) Port control register
Figure 2.16.9 shows the port control register. The bit 0 of port control resister is used to read port P1 as follows: 0 : When port P1 is input port, port input level is read. When port P1 is output port , the contents of port P1 register is read. 1 : The contents of port P1 register is read always. In memory expansion mode, this register is valid in the following: * External bus width is 8 bits. * Port P1 can be used as a port in multiplexed bus for the entire space.
Rev. 1.0
170
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Pull-up selection Direction register P00 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P54, P56 Data bus Port latch
VCC VSS
(Note1)
Pull-up selection P10 to P14 Direction register
Port P1 control register
Data bus
Port latch (Note1)
Pull-up selection P15 to P17 Direction register
Port P1 control register
Data bus
Port latch (Note1)
Input to respective peripheral functions Pull-up selection P57, P60, P61, P64, P65, P72 to P76, P80, P81, P90, P92 Data bus Direction register
"1"
Output
Port latch (Note1)
Input to respective peripheral functions
Note1 :
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port.
Figure 2.16.1 Programmable I/O ports (1)
Rev. 1.0
171
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Pull-up selection P82 to P84 Direction register
VCC VSS
Data bus
Port latch (Note1)
Input to respective peripheral functions Pull-up selection Direction register P55, P62, P66, P77, P91, P97 Data bus Port latch (Note1)
Input to respective peripheral functions Pull-up selection P63, P67 Direction register "1" Data bus Port latch Output (Note1)
P85 Data bus NMI interrupt input (Note1)
P70, P71
Direction register "1" Port latch Output (Note1)
Data bus
Input to respective peripheral functions
Note1 :
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port.
Figure 2.16.2 Programmable I/O ports (2)
Rev. 1.0
172
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
VCC
P100 to P103 (inside dotted-line not included) P104 to P107 (inside dotted-line included)
Pull-up selection
VSS
Direction register
Data bus
Port latch (Note1)
Analog input Input to respective peripheral functions
Pull-up selection D-A output enabled P93, P94 Direction register
Data bus
Port latch (Note1)
Input to respective peripheral functions Analog output D-A output enabled Pull-up selection Direction register P96 "1" Data bus Port latch Output (Note1)
Analog input Pull-up selection Direction register P95 "1" Data bus Port latch Output (Note1)
Input to respective peripheral functions Analog input Note1 : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port.
Figure 2.16.3 Programmable I/O ports (3)
Rev. 1.0
173
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Pull-up selection
Direction register
Data bus
Port latch
(Note1)
Pull-up selection
Direction register "1"
Output Data bus Port latch
(Note1)
Note1 :
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port.
Figure 2.16.4 Programmable I/O ports (4)
VCC
BYTE
VSS
BYTE signal input (Note)
CNVSS
CNVSS signal input (Note)
RESET
RESET signal input
(Note)
M1
VCC
Input (Note)
VSS
to internal circuit
M2
VCC
to flash memory (Power supply for fash memory rewriting) to flash memory (Note)
Input
VSS
Note :
symbolizes a parasitic diode. Do not apply a voltage higher than VCC to each pin.
Figure 2.16.5 I/O pins
Rev. 1.0
174
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Port Pi direction register (Note 1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PDi (i = 0 to 10, except 8) Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F316, 03F616 Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 10 except 8)
When reset 0016 0016
Bit name
Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register
RW
Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting to the port P9 direction register. Note 2: In memory expansion mode, the contents of corresponding port Pi direction register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified.
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address 03F216 Bit name
Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register
When reset 00X000002 Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
Bit symbol
PD8_0 PD8_1 PD8_2 PD8_3
RW
PD8_4 Port P84 direction register Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. PD8_6 PD8_7 Port P86 direction register Port P87 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
Figure 2.16.6 Direction register
Rev. 1.0
175
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Port Pi register (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Pi (i = 0 to 10, except 8)
Address 03E016, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F116, 03F416 Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (Note) (i = 0 to 10 except 8)
When reset Indeterminate Indeterminate RW
Bit symbol
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Bit name
Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register
Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance. Note 2: In memory expansion mode, the contents of corresponding port Pi direction register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified.
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P8 Bit symbol
P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7
Address 03F016 Bit name
Port P80 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register
When reset Indeterminate Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : "L" level data 1 : "H" level data
RW
Figure 2.16.7 Port register
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0
Bit symbol
PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07
Address 03FC16
Bit name
P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up
When reset 0016
Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1
Bit symbol
PU10 PU11 PU12 PU13 PU14 PU15 PU16 PU17
Address 03FD16
Bit name
P40 to P43 pull-up P44 to P47 pull-up P50 to P53 pull-up P54 to P57 pull-up P60 to P63 pull-up P64 to P67 pull-up P70 to P73 pull-up (Note 1) P74 to P77 pull-up
When reset 0016
Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: In memory expansion mode, the content of these bits can be changed,but the pull-up resistance is not connected.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR2
Bit symbol
PU20 PU21 PU22 PU23 PU24 PU25
Address 03FE16
Bit name
P80 to P83 pull-up P84 to P87 pull-up (Except P85) P90 to P93 pull-up P94 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up
When reset 0016
Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Figure 2.16.8 Pull-up control register
Rev. 1.0
177
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl PCR
Address 03FF16
When reset 0016
Bit symbol
PCR0
Bit name
Port P1 control register
Function
0 : When input port, read port input level. When output port, read the contents of port P1 register. 1 : Read the contents of port P1 register though input/output port.
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Figure 2.16.9 Port control register
Rev. 1.0
178
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 2.16.1 Example connection of unused pins in single-chip mode
Pin name Ports P0 to P10 (excluding P85) XOUT(Note) NMI AVCC AVSS, VREF, BYTE Connection After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. Open Connect via register to VCC (pull-up) Connect to VCC Connect to VSS
Note: With external clock input to XIN pin.
Table 2.16.2 Example connection of unused pins in memory expansion mode
Pin name Ports P6 to P10 (excluding P85) P45/CS1 to P47/CS3 Connection After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. Sets ports to input mode, sets bits CS1 through CS3 to 0, and connects to Vcc via resistors (pull-up). Open
BHE, ALE, HLDA, XOUT(Note1), BCLK(Note2) HOLD, RDY, NMI AVCC AVSS, VREF
Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS
Note 1: With external clock input to XIN pin. Note 2: When the BCLK output disable bit (bit 7 at address 000416) is set to "1", connect to VCC via a resistor (pull-up).
Microcomputer
Port P0 to P10 (except for P85) (Input mode)
Microcomputer
Port P6 to P10 (except for P85) (Input mode)
.. .
...
.. .
(Input mode) (Output mode)
(Input mode)
Open
(Output mode)
Open
NMI NMI XOUT Open VCC AVCC BYTE AVSS VREF Port P45 / CS1 to P47 / CS3 BHE HLDA ALE XOUT BCLK HOLD RDY CNVSS AVCC VSS In single-chip mode AVSS VREF In memory expamsion mode or in microprossor mode VSS
...
Open VCC
0.47F
Note : When the BCLK output disable bit (bit7 at address 000416) is set to "1", connet to VCC via a resistor (pull-up)
Figure 2.16.10 Example connection of unused pins
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
3. USAGE PRECAUTION Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets "FFFF16". Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets "FFFF16" by underflow or "000016" by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. (3) In the case of using "Event counter mode" as "Free-Run type" for timer A, the timer register contents may be unkown when counting begins. If the timer register is set before counting has started, then the starting value will be unkown. This issue will occuer only for the "Event counter mode" operating as "Free-Run type". The value of the timer register will not be unkown during counting.
Timer A (one-shot timer mode)
(1) Setting the count start flag to "0" while a count is in progress causes as follows: * The counter stops counting and a content of reload register is reloaded. * The TAiOUT pin outputs "L" level. * The interrupt request generated and the timer Ai interrupt request bit goes to "1". (2) The timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the following procedures: * Selecting one-shot timer mode after reset. * Changing operation mode from timer mode to one-shot timer mode. * Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures: * Selecting PWM mode after reset. * Changing operation mode from timer mode to PWM mode. * Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made. (2) Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an "H" level in this instance, the output level goes to "L", and the timer Ai interrupt request bit goes to "1". If the TAiOUT pin is outputting an "L" level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes "1".
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets "FFFF16". Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to "1". (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from "0" to "1", start A-D conversion after an elapse of 1 s or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-D conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to "L" level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to "1" within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to "1". (3) When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with WAIT periphheral function clock stop bit set to "1".
Interrupts
(1) Reading address 0000016 * When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0". Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0". Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer * The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. _______ When using the NMI interrupt, initialize the stack point at the beginning of _______ a program. Concerning the first in struction immediately after reset, generating any interrupts including the NMI interrupt is prohib ited.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
_______
(3) The NMI interrupt
_______
* As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor (pull-up) if unused. Be sure to work on it.
_______
* Do not get either into stop mode with the NMI pin set to "L". (4) External interrupt
________ ________
* When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". (5) Rewrite the interrupt control register * To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
* When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version.
Rev. 1.0
182
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Other Notes
(1) Timing of power supplying The power need to supply to VCC, VDD1, VDD2, VDD3 and AVCC at a time. While operating, must set same voltage.
(2) Power supply noise and latch-up In order to avoid power supply noise and latch-up, connect a bypass capacitor (more than 0.1F) directly between the VCC pin and VSS pin, VDD1 pin and VSS1 pin, VDD2 pin and VSS2 pin, VDD3 pin and VSS3 pin, AVCC pin and AVSS pin using a heavy wire.
(3) When oscillation circuit stop for data slicer Expansion register XTAL-VCO, PDC_VCO_ON,VPS_VCO_ON is set at "L", when the data slicer is not used, and the oscillation is stopped. When starting oscillation again, set data at the folowing order. (a) Set expansion register XTAL-VCO = "H". (b) Set expansion register PDC_VCO_ON,VPS_VCO_ON = "H". (c) 60 ms or more is a waiting state (stability period of internal oscillation circuit + data slice preparation). To operate slice RAM , set expansion register XTAL_VCO = "H". And input 4.43 MHz sub carrier frequency clock from the FSCIN pin. Access the memories after wating for 20 ms certainly when resuming synchronous oscillation from the off state , and begin to input clock into the FSCIN pin.
(4) At stop mode (clock is stopped) Set each input pins to as follows. (a) Set M1 pin = VSS. (b) Stop the FSCIN pin input. (c) Set expansion register STBY0 and STBY1 = "H". Set all expansion registers to "L" except for the superscription register.
(5) When operation start from stand-by mode (clock is stopped) Input FSCIN pin clock after set "L" to register STBY0 and STBY1. At next, set expansion register as notes (3).
Rev. 1.0
183
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
(6) Notes on operating with a low supply voltage (VCC = 3.0 V) When in single-chip mode, this product can operate with a low supply voltage (VCC = 3.0 V) only during low power dissipation mode. Before operating with a low supply voltage, always be sure to set the relevant register bits to select low power dissipation mode (BCLK : f(XCIN), main clock XIN : stop, subclock XCIN : oscillating). Then reduce the power supply voltage VCC to 3.0 V. Also, when returning to normal operation, raise the power supply voltage to 5V while in low power consumption mode before entering normal operation mode. When moving from any operation mode to another, make sure a state transition occurs according to the state transition diagram (Figure 2.5.5) in Section 2.5.7, "Power control." The status of the power supply voltage VCC during operation mode transition is shown in Figure 3.1 below.
5V VCC 3V
Power control operation modes
Normal operation mode
Low power dissipation mode
Normal operation mode
Note 1: Normal operation mode refers to the high-speed, medium-speed, and low-speed modes. Note 2: When operating with a low supply voltage, be aware that only the CPU, ROM, RAM, input/output ports, timers (timers A and B), and the interrupt control circuit can be used. All other internal resources (e.g., data slicer, DMAC, A/D, and D/A) cannot be used.
Figure 3.1 Status of the power supply voltage VCC during operation mode transition
Rev. 1.0
184
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
4. ELECTRICAL CHARACTERISTICS
Table 4.1 Absolute maximum ratings
Symbol
Vcc AVcc M2 Supply voltage Analog supply voltage Supply voltage for program/erase RESET, CNVss, BYTE, P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, VREF, XIN, M1 P70, P71 Output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37,P40 to P47, P50 to P57, P60 to P67,P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, XOUT, P11 P70, P71 Power dissipation Operating ambient temperature Storage temperature
Parameter
Condition
VCC=AVCC VCC=AVCC
Rated value
-0.3 to 5.75 -0.3 to 5.75
Unit
V V V
-0.3 to 5.75
Input voltage
VI
-0.3 to Vcc+0.3
V
-0.3 to 5.75
V
VO
-0.3 to Vcc+0.3
V
Pd Topr Tstg
Ta=25 C
-0.3 to 5.75 1000 -20 to 70 -40 to 125
V mW C C
Rev. 1.0
185
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Tabl 4.2 Recommended operating conditions (referenced to VCC = 4.75V to 5.25V at Ta = - 20 to 70oC unless otherwise specified)
Symbol
Vcc AVcc Vss AVss
Parameter
Supply voltage Analog supply voltage Supply voltage Analog supply voltage
HIGH input P70 to P77, P80 to P87, P90 to P97, P100 to P107, P31 to P37, P40 to P47, P50 to P57, P60 to P67, voltage XIN, RESET, CNVSS, BYTE, M1, P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode)
P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion mode) LOW input voltage
P70 to P77, P80 to P87, P90 to P97, P100 to P107, P31to P37, P40 to P47, P50 to P57, P60 to P67, XIN, RESET, CNVSS, BYTE, M1 P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion mode)
Min
4.75
Standard Typ. Max.
5.0 Vcc 0 0 5.25
Unit
V V V V V
V
V
VIH
0.8Vcc
0.8Vcc
0.5Vcc
Vcc
Vcc
Vcc
0 0 0
2V P-P 0.3V P-P
0.2Vcc 0.2Vcc 0.16Vcc
V V
V
VIL
VCVIN VFSCIN
Composite video input voltage Input voltage
CVIN, SYNCIN
V 4.0V P-P V
I OH (peak)
I OH (avg)
I OL (peak)
I OL (avg)
FSCIN(Note 1) P00to P07, P10 to P17,P20 to P27, P30 to P37, HIGH peak output P40 to P47, P50 to P57,P60 to P67, P72 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107, (Note 2.3) P11 HIGH average output P00 to P07, P10 to P17,P20 to P27,P30 to P37, P40 to P47, P50 to P57,P60 to P67,P72 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107, P11 P00 to P07, P10 to P17,P20 to P27,P30 to P37, LOW peak output P40 to P47, P50 to P57, P60 to P67,P70 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107, P11 LOW average P00 to P07, P10 to P17,P20 to P27,P30 to P37, output current P40 to P47, P50 to P57,P60 to P67,P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, P11,
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
f (XIN) f (XcIN)
Main clock input oscillation frequency
No wait with wait
Vcc=4.75V to 5.25V
0
10
MHz kHz
MHz
Vcc=2.80V to 5.25V (see note 4) Subclock oscillation frequency f (FSCIN) Oscillation frequency for synchronous signal(Duty 40% to 60%)
32.768
4.434
50
Note 1: Noise component is within 30mV. Note 2: The mean output current is the mean value within 100ms. Note 3: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max. Note 4: Use the low power dissipation mode.
Rev. 1.0
186
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 4.3 Electrical characteristics (1)VCC = 5V (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) =10MHZ unless otherwise specified)
Symbol
VOH
Parameter
Measuring condition
Standard Min Typ. Max.
3.0
Unit
HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH=-5mA P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, P11 HIGH output P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, voltage P60 to P67, P72 to P77, P80 to P84, IOH=-200A P86, P87, P90 to P97, P100 to P107, P11 HIGH output LP2 to LP4 voltage HIGH output voltage HIGH output voltage XOUT XCOUT
HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER
V
VOH
4.7
V
VOH
VCC=4.75V, I OH=-0.05mA IOH=-1mA IOH=-0.5mA
3.75 3.0 3.0 3.0 1.6
V V V
VOH
With no load applied With no load applied
IOL=5mA
VOL
LOW output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, P11 LOW output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, P11 LOW output LP2 to LP4 voltage LOW output voltage LOW output voltage Hysteresis XOUT XCOUT
HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER
2.0
V
VOL
IOL=200A
0.45
V
VOL VOL
VCC=4.75V, I OL=0.05mA IOL=1mA IOL=0.5mA
0.4 2.0 2.0 0 0
V V V
With no load applied With no load applied
0.2
VT+-VT-
HOLD, RDY, TA0IN to TA4 IN, TB0IN to TB2IN, INT0 to INT5, ADTRG, CTS1, CLK1, NMI TA2 OUT to TA4 OUT,KI0 to KI3 CTS0, CLK0 RESET
0.8
V
VT+-VTVT+-VT-
Hysteresis Hysteresis
0.2 0.2
1.4 1.8
V V
IIH
HIGH input P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, current P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE, M1 LOW input current P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE, M1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107
VI=5V
5.0
A
I IL
VI=0V
-5.0
A
RPULLUP
Pull-up resistance
VI=0V
30.0
50.0
167.0
k V V %
V SYNCIN V dat(text) f/ f fH
Sync voltage amplitude Teletext data voltage amplitude Range for display oscillator circuit Horizontal synchronous signal frequency
0.3 0.6 7 14.6
0.6 0.9
1.2 1.4
15.625
17.0
kHZ
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 4.4 Electrical characteristics (2)VCC = 3V (referenced to VCC=3V,VSS=0V,Ta=25C, f(XCIN)=32KHZ unless otherwise specified)
Symbol
VOH
Parameter
HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P11 HIGH output voltage XCOUT
HIGHPOWER LOWPOWER
Measuring condition
Min
2.5
Standard Typ. Max. Unit
V
IOH= -150A
VOH
With no load applied With no load applied
3.0 1.6 V
VOL
LOW output P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, voltage P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P11 LOW output voltage Hysteresis XCOUT
HIGHPOWER LOWPOWER
IOL=150A
0.5
V
VOL
With no load applied With no load applied
0.2
0 0 0.8 V
VT+-VTHIGH input voltage IIH
TA0IN to TA4IN, TB0IN to TB2IN, INT0 to INT5, TA2OUT to TA4OUT, NMI, KI0 to KI3 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE, M1
V
VI=3V
4.0
A
LOW input voltage IIL
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, VI=0V P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE, M1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, VI=0V P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107
-4.0
A
RPULLUP
Pull-up resistance
66.0
120.0
500.0
k
Rev. 1.0
188
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 4.5 Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Symbol
RfXIN RfXCIN V
RAM
Parameter
Feedback resistance XIN Feedback resistance XCIN RAM retention voltage Power supply current
Measuring condition
Min
Standard Typ. Max.
1.0 6.0
Unit
M M V
mA A
A
When clock is stopped
At the time of slicer operation f(XCIN)=10kHz VCC=5.0V f(XCIN)=32kHz A rectangular wave (Notes 1, 2) VCC=3.0V f(XCIN)=32kHz A rectangular wave (Notes 1, 2) VCC=5.0V f(XCIN)=32kHz At the time of weight (Notes 1, 2) VCC=3.0V f(XCIN)=32kHz At the time of weight (Notes 1, 2)
At the time of a clock stop (Notes 2)
2.0
I cc
150
200 150
5.0
180
10.0
8.0
5.0
A
A
A
3.0
Note 1: This is a state where only one timer is operating with fc32 while the oscillation capability is set to LOWand slicer operation is turned OFF. Note 2: * VDD1, VDD2, and VDD3 all are at the same potential level as VCC. * Extension register (address 0016 DD8) STBY0 and (address 1516 DD13) STBY1 are set to 1 while all other extension registers (addresses 0016 through 2216) are set to 0. * Clock input to the FSCIN pin is disabled. * Inputs to the SYNCIN and CVIN1 pins are disabled.
Tabl 4.6 Video signal input conditions (VCC = 5.0V, Ta = -20 to 70oC)
Symbol
VIN-cu
Parameter
Composite video signal input clamp voltage
Measuring condition
Sync-chip voltage
Min
Standard Typ. Max.
1.0
Unit
V
Rev. 1.0
189
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 4.7 A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Symbol Resolution
Absolute accuracy
Sample & hold function not available
Sample & hold function available(8bit)
Parameter
Measuring condition
VREF = VCC VREF = VCC = 5V VREF = VCC = 5V VREF = VCC
Standard Min. Typ. Max. Unit
8 3 2 40 Bits LSB LSB k
s s V V
RLADDER tCONV tSAMP VREF VIA
Ladder resistance Conversion time(8bit) Sampling time Reference voltage Analog input voltage
10 2.8 0.3 2 0
VCC VREF
Table 4.8 D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Symbol Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Measuring condition
Standard Min. Typ. Max. 8 1.0 3 4 10 20 1.5
Unit
Bits % s k mA
tsu RO IVREF
(Note)
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "0016". The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
Rev. 1.0
190
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 4.9 External clock input
Symbol
tc tw(H) tw(L) tr tf
Parameter
External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time
Standard Min. Max.
100 40 40 18 18
Unit
ns ns ns ns ns
Table 4.10 In memory expansion mode
Symbol
tac1(RD-DB) tac2(RD-DB) tac3(RD-DB)
Parameter
Data input access time (no wait) Data input access time (with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time
Standard Min. Max.
(Note) (Note) (Note)
40 30 40 0 0 0 40
Unit
ns ns ns
tsu(DB-RD) tsu(RDY-BCLK )
tsu(HOLD-BCLK )
ns ns ns ns ns
ns
ns
th(RD-DB) th(BCLK -RDY)
th(BCLK-HOLD ) td(BCLK-HLDA )
Note: Calculated according to the BCLK frequency as follows:
tac1(RD - DB) =
tac2(RD - DB) =
tac3(RD - DB) =
10 9 - 45 f(BCLK) X 2
3 X 10 - 45 f(BCLK) X 2
3 X 10 - 45 f(BCLK) X 2
9
[ns]
9
[ns]
[ns]
Rev. 1.0
191
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 4.11 Timer A input (counter input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 Unit ns ns ns
Table 4.12 Timer A input (gating input in timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns
Table 4.13 Timer A input (external trigger input in one-shot timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 200 100 100 Unit ns ns ns
Table 4.14 Timer A input (external trigger input in pulse width modulation mode)
Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 100 100 Unit ns ns
Table 4.15 Timer A input (up/down input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns
Rev. 1.0
192
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 4.16 Timer B input (counter input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 4.17 Timer B input (pulse period measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns
Table 4.18 Timer B input (pulse width measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns
Table 4.19 A-D trigger input
Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns
Table 4.20 Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time
_______
Parameter
Standard Min. 200 100 100 80 0 30 90 Max.
Unit ns ns ns ns ns ns ns
Table 4.21 External interrupt INTi inputs
Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 250 250 Max. Unit ns ns
Rev. 1.0
193
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = "1" unless otherwise specified) Table 4.22 In memory expansion mode (No wait)
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB)
Parameter
Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 10 9 - 40 f(BCLK) X 2
Measuring condition
Standard Min. Max.
40 4 0 0 40 4 40
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 4.1
-4 40 0 40 0 40 4
(Note1)
0
Note 1: Calculated according to the BCLK frequency as follows:
td(DB - WR) = [ns]
Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC / VCC) = 6.7ns.
R DBi C
Rev. 1.0
194
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Switching characteristics (refer to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = "1" unless otherwise specified) Table 4.23 In memory expansion mode (With wait, accessing external memory) Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB)
Parameter
Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 10 9 f(BCLK)
Measuring condition
Standard Min. Max.
40 4 0 0 40 4 40 -4 40 0 40 0 40 4 (Note1) 0
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 4.1
Note 1: Calculated according to the BCLK frequency as follows:
td(DB - WR) = - 40 [ns]
Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC / VCC) = 6.7ns.
R DBi C
Rev. 1.0
195
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = "1" unless otherwise specified) Table 4.24 In memory expansion mode (With wait, accessing external memory, multiplex bus area selected)
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD)
Parameter
Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (Address standard) ALE signal output hold time (Adderss standard) Post-address RD signal output delay time Post-address WR signal output delay time Address output floating start time 10 f(BCLK) X 2
10 f(BCLK) X 2
10 f(BCLK) X 2
10 f(BCLK) X 2
10 X 3 - 40 f(BCLK) X 2
10 f(BCLK) X 2
9
Measuring condition
Standard Min. Max.
40 4
(Note) (Note)
Unit
ns ns ns ns ns ns ns ns
40 4
(Note) (Note)
40 0 40
Figure 4.1
0 40 4
(Note) (Note)
ns ns ns ns ns ns ns ns
40 -4
(Note)
50 0 0 8
ns ns ns ns ns ns ns
Note: Calculated according to the BCLK frequency as follows:
9
th(RD - AD) =
[ns]
9
th(WR - AD) =
[ns]
9
th(RD - CS) =
[ns]
9
th(WR - CS) =
[ns]
9
td(DB - WR) =
[ns]
th(WR - DB) =
[ns]
td(AD - ALE) =
10 - 40 f(BCLK) X 2
9
[ns]
Rev. 1.0
196
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11
30pF
Figure 4.1 Port P0 to P11 measurement circuit
Rev. 1.0
197
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input
(When count on falling edge is selected)
th(TIN-UP)
tsu(UP-TIN)
TAiIN input
(When count on rising edge is selected)
tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q)
Figure 4.2 Timing diagram (1)
Rev. 1.0
198
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
In memory expansion mode Valid Only With Wait
BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input
tsu(RDY-BCLK) th(BCLK-RDY)
Valid With Or Without Wait
BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD)
HLDA output td(BCLK-HLDA) P0, P1, P2, P3, P4, P50 to P52
Hi-Z
td(BCLK-HLDA)
Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43. Measuring conditions : * VCC=5V * Input timing voltage : Determined with VIL=1.0V, VIH=4.0V * Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 4.3 Timing diagram (2)
Rev. 1.0
199
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
In memory expansion mode (With No Wait)
Read timing
BCLK td(BCLK-CS)
40ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi BHE ALE RD
td(BCLK-ALE) th(BCLK-ALE)
25ns.max 40ns.max -4ns.min
th(RD-AD)
0ns.min
td(BCLK-RD)
th(BCLK-RD)
0ns.min
tac1(RD-DB) DB
Hi-Z
tSU(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing BCLK td(BCLK-CS)
40ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
th(WR-CS)
0ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi BHE ALE
td(BCLK-ALE) th(BCLK-ALE)
40ns.max
th(WR-AD) 0ns.min th(BCLK-WR)
0ns.min
-4ns.min
td(BCLK-WR) WR,WRL, WRH DB
40ns.max
td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
(tcyc/2-40)ns.min
td(DB-WR)
th(WR-DB)
0ns.min
Figure 4.4 Timing diagram (3)
Rev. 1.0
200
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
In memory expansion mode (When Accessing External Memory Area With Wait) Read timing BCLK td(BCLK-CS)
40ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi BHE ALE
td(BCLK-ALE) 40ns.max
th(RD-AD)
0ns.min
th(BCLK-ALE)
-4ns.min
td(BCLK-RD) RD DB
40ns.max
th(BCLK-RD)
0ns.min
tac2(RD-DB)
Hi-Z
tSU(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing BCLK td(BCLK-CS)
40ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
th(WR-CS)
0ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi BHE ALE
td(BCLK-ALE)
40ns.max
th(WR-AD)
0ns.min
th(BCLK-ALE)
-4ns.min
td(BCLK-WR) WR,WRL, WRH DBi td(DB-WR)
(tcyc-40)ns.min 40ns.max
th(BCLK-WR)
0ns.min
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
th(WR-DB)
0ns.min
Measuring conditions : * VCC=5V * Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V * Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V
Figure 4.5 Timing diagram (4)
Rev. 1.0
201
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
In memory expansion mode (When Accessing External Memory Area With Wait, And Select Multiplexed bus) Read timing BCLK td(BCLK-CS)
40ns.max tcyc
th(RD-CS)
(tcyc/2)ns.min
th(BCLK-CS)
4ns.min
CSi ADi /DBi
td(AD-ALE)
(tcyc/2-40)ns.min Address
th(ALE-AD)
30ns.min Data input tac3(RD-DB) Address
tdz(RD-AD)
8ns.max
th(RD-DB) tSU(DB-RD) 0ns.min
40ns.min
td(AD-RD)
0ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi BHE ALE RD
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
(tcyc/2)ns.min
td(BCLK-RD)
40ns.max
th(BCLK-RD)
0ns.min
Write timing BCLK td(BCLK-CS)
40ns.max tcyc
th(BCLK-CS) th(WR-CS)
(tcyc/2)ns.min 4ns.min
CSi td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min Data output Address
ADi /DBi
Address
td(AD-ALE)
(tcyc/2-40)ns.min
td(DB-WR)
(tcyc*3/2-40)ns.min
th(WR-DB)
(tcyc/2)ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi BHE ALE
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
td(AD-WR)
0ns.min
th(WR-AD)
(tcyc/2)ns.min
td(BCLK-WR) WR,WRL, WRH
40ns.max
th(BCLK-WR)
0ns.min
Measuring conditions : * VCC=5V * Input timing voltage : Determined with VIL=0.8V, VIH=2.5V * Output timing voltage : Determined with VOL=0.8V, VOH=2.0V
Figure 4.6 Timing diagram (5)
Rev. 1.0
202
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5. FLASH MEMORY 5.1 Outline Performance
Table 5.1.1 shows the outline performance of the M306H2FCFP (flash memory version). Table 5.1.1. Outline performance of the M306H2FCFP (flash memory version)
Item Power supply voltage Program/erase voltage Flash memory operation mode Erase block division User ROM area Boot ROM area Performance 4.75V to 5.25 V (at f(X IN) = 10 MHz) 4.75V to 5.25 V (f(XIN) = 10 MHz, No wait, f(XIN) = 5 MHz, One wait) Three modes (parallel I/O, standard serial I/O, CPU rewrite) Refer to Figure 5.2.1 No division (8 K bytes) (Note 1) In units of words Collective erase/block erase Program/erase control by software command 6 commands 100 times Parallel I/O and standard serial I/O modes are supported.
Program method Erase method Program/erase control method Number of commands Program/erase count ROM code protect
Note : The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode.
Rev. 1.0
203
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.2 Flash Memory mode
The M306H2FCFP (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory is divided into several blocks as shown in Figure 5.2.1, so that memory can be erased one block at a time. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user's application system. This boot ROM area can be rewritten in only parallel I/O mode.
0DE00016 0DFFFF16 0E000016
Boot ROM area Block 3 : 32K byte Block 2 : 32K byte
8K byte
0E800016 0F000016
Flash memory size 128K Flash memory start address 0E000016
User ROM area Block 1 : 32K byte Block 0 : 32K byte Note 1: The boot ROM area can be rewritten in only parallel input/ output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the optional even address in the block.
0F800016 0FFFFF16
byte
Figure 5.2.1. Block diagram of flash memory version
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.3 CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 5.2.1 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. (1) Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 5.2.1 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the M1 pin low, the CNVSS pin high, the P50 pin high, the CPU starts operating using the control program in the boot ROM area (program start address is DE00016 fixation). This mode is called the "boot" mode. (2) Block Address Block addresses refer to the optional even address of each block. These addresses are used in the block erase command.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.3.1 Outline Performance (CPU Rewrite Mode) In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM before it can be excuted. The CPU rewrite mode is accessed by applying 5V 5% to the M2 pin and writing "1" for the CPU rewrite mode select bit (bit 1 in address 03B416). Software commands are accepted once the mode is accessed. In the CPU rewrite mode, write to and read from software commands and data into even-numbered address ("0" for byte address A0) in 16-bit units. Always write 8-bit software commands into evennumbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 5.3.1 shows the flash memory control register.
_____
Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is "0". Otherwise, it is "1". Bit 1 is the CPU rewrite mode select bit. When this bit is set to "1" and 5V 5% are applied to the M2 pin, the M306H2 accesses the CPU rewrite mode. Software commands are accepted once the mode is accessed. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in RAM for write to bit 1. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. The bit can be set to "0" by only writing a "0" . Bit 2 is the CPU rewrite mode entry flag. This bit can be read to check whether the CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is "1", writing "1" for this bit resets the control circuit. To release the reset, it is necessary to set this bit to "0". If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. Figure 5.3.2 shows a flowchart for setting/releasing the CPU rewrite mode.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMCR Bit symbol
Address
03B416
When reset
XXXX00012
Bit name RY/BY status flag CPU rewrite mode select bit (Note 1)
Function 0: Busy (being written or erased) 1: Ready 0: Normal mode (Software commands invalid) 1: CPU rewrite mode 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) 0: Normal operation 1: Reset
RW RW
FMCR0 FMCR1
FMCR2
CPU rewrite mode entry flag
FMCR3
Flash memory reset bit (Note 2)
Nothing is assigned. When write, set "0". When read, values are indeterminate. Note 1: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Use the control program in the RAM for write to this bit. Note 2: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently after setting it to 1 (reset).
Figure 5.3.1. Flash memory control registers
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Program in ROM
Start
Single-chip mode, or boot mode (Note 1)
Set processor mode register (Note 2)
Transfer CPU rewrite mode control program to internal RAM
Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM)
Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession)(Note 3)
Check the CPU rewrite mode entry flag
Using software command execute erase, program, or other operation
Execute read array command or reset flash memory by setting flash memory reset bit (by writing "1" and then "0" in succession) (Note 4)
Write "0" to CPU rewrite mode select bit
End
Notes 1: Apply 5V 5 % to M2 pin by confirmation of CPU rewrite mode entry flag when started operation with single-chip mode. 2: During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 5.0 MHz or less when wait bit (bit 7 at address 000516) = "0" (without internal access wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = "1" (with internal access wait state) 3: For CPU rewrite mode select bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. 4: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory.
Figure 5.3.2. CPU rewrite mode set/reset flowchart
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.3.2 Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 5.0 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state) (2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use _______ The NMI, address match, and watchdog timer interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be used by transferring the vector into the RAM area. (4) Reset If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. Set a 5 ms wait to release the reset operation. Also, when the reset has been released, the program execute start address is automatically set to 0DE00016 at boot mode, therefore program so that the execute start address of the boot ROM is 0DE00016. (5) Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O mode to rewrite these blocks.
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209
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.3.3 Software Commands Table 5.3.1 lists the software commands available with the M306H2 (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored. The content of each software command is explained below. Table 5.3.1. List of software commands (CPU rewrite mode)
First bus cycle Command Read array Read status register Clear status register Program
(Note 3)
Second bus cycle Mode Address Data (D0 to D7)
Cycle number 1 2 1 2 2 2
Mode Write Write Write Write Write Write
Data Address (D0 to D7) X
(Note 5)
FF16 7016 5016 4016 2016 2016 Write Write Write BA WA
(Note 3)
X X X X X
Read
X
SRD
(Note 2)
WD 2016 D016
(Note 3)
Erase all block Block erase
X
(Note 4)
Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored. Note 2: SRD = Status Register Data Note 3: WA = Write Address, WD = Write Data Note 4: BA = Block Address (Enter the optional address of each block that is an even address.) Note 5: X denotes a given address in the user ROM area (that is an even address).
Read Array Command (FF16) The read array mode is entered by writing the command code "FF16" in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D0-D15), 16 bits at a time. The read array mode is retained intact until another command is written. Read Status Register Command (7016) When the command code "7016" is written in the first bus cycle, the content of the status register is read out at the data bus (D0-D7) by a read in the second bus cycle. The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR4 to SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code "5016" in the first bus cycle.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Program Command (4016) Program operation starts when the command code "4016" is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by reading the status register or the RY/ _____ BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (D0 - D7). The status register bit 7 (SR7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. In this case, the read status register mode remains active until the Read Array command (FF16) is written. ____ The RY/BY status flag is 0 during write operation and 1 when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Erase All Blocks Command (2016/2016) By writing the command code "2016" in the first bus cycle and the confirmation command code "2016" in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify). Whether the erase all blocks command is terminated can be confirmed by reading the status register ____ or the RY/BY status flag. When the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the erase operation starts and is returned to 1 upon completion of the erase operation. In this case, the read status register mode remains active until the Read Array command (FF16) is written.
Start Write 4016 Write Write address Write data Status register read
SR7=1? or RY/BY=1? YES
NO
NO SR4=0? YES Program completed
Program error
Figure 5.3.3. Program flowchart
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
____
The RY/BY status flag is 0 during erase operation and 1 when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Block Erase Command (2016/D016) By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. Whether the block erase operation is completed can be confirmed by reading the status register or the ____ RY/BY status flag. At the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. In this case, the read status register mode remains active until the Read Array command (FF16). ____ The RY/BY status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status register bit 7. After the block erase operation is completed, the status register can be read out to know the result of the block erase operation. For details, refer to the section where the status register is detailed.
Start
Write 2016
Write
2016/D016 Block address
2016:Erase all blocks D016:Block erase
Status register read
SR7=1? or RY/BY=1?
NO
YES SR5=0? YES Erase completed NO Erase error
Figure 5.3.4. Erase flowchart
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.3.4 Status Register The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways. (1) By reading an arbitrary address from the user ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the user ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input Table 5.3.2 shows the status register. Also, the status register can be cleared in the following way. (1) By writing the clear status register command (5016) After a reset, the status register is set to "8016". Each bit in this register is explained below. Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. Erase status (SR5) The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set to 1. The erase status is reset to 0 when cleared. Program status (SR4) The program status informs the operating status of write operation to the CPU. When a write error occurs, it is set to 1. The program status is reset to 0 when cleared. If "1" is written for any of the SR5 or SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, any commands are not correct, both SR5 and SR4 are set to 1.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 5.3.2. Definition of each bit in status register
Each bit of SRD SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0)
Definition Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -
5.3.5 Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 5.3.5 shows a full status check flowchart and the action to be taken when each error occurs.
Read status register
YES SR4=1 and SR5 =1 ? NO
Command sequence error (Note 1)
Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used.
SR5=0? YES
NO
Block erase error
SR4=0? YES
NO
Program error
Should a program error occur, the block in error cannot be used.
End (block erase, program)
Note 1: Either SR5 or SR4 may become "0". Take care about it during program debugging. Note 2: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands.
Figure 5.3.5. Full status check flowchart and remedial procedure for errors
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.4 Functions To Inhibit Rewriting Flash Memory Version
To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. 5.4.1 ROM code protect function The ROM code protect function is used to prohibit reading out or modifying the contents of the flash memory during parallel I/O mode and is set by using the ROM code protect control address register (0FFFFF16). Figure 5.4.1 shows the ROM code protect control address (0FFFFF16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to "00," ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ROMCP
Address 0FFFFF16
When reset FF16
Bit symbol
Bit name
Function Always set this bit to 1.
b3 b2
Reserved bit
ROMCP2
ROM code protect level 2 set bit (Note 1, 2)
00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled
b5 b4
ROMCR
ROM code protect reset bit (Note 3)
00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective
b7 b6
ROMCP1
ROM code protect level 1 set bit (Note 1)
00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be changed in parallel input/ output mode, they need to be rewritten in serial input/output or some other mode.
Figure 5.4.1. ROM code protect control address
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.4.2 ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector
4 bytes
Figure 5.4.2. ID code store addresses
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.5 Parallel I/O Mode
The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is parallel. Use an exclusive programer supporting M306H2 (flash memory version). Refer to the instruction manual of each programer maker for the details of use.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 5.2.1 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 5.2.1. The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0DE00016 through 0DFFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.6 Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting "H" to the CNVSS pin and P50 pin, connecting "L" to the M1 pin, and releasing the reset operation. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figure 5.6.1 shows the pin connections for the standard serial I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK1 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and release the reset. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "L" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the reset. The operation uses the two UART1 pins RxD1 and TxD1. In the standard serial I/O mode, only the user ROM area indicated in Figure 5.2.1 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Pin functions (Flash memory standard serial I/O mode) (Note 1)
Pin VCC,VSS CNVSS RESET M1 M2 BYTE XIN XOUT AVCC, AVSS VREF P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 P51 to P57 P60 to P63 P64 P65 P66 P67 P70 to P77
P80 to P84,P86,P87
Name Power input CNVSS Reset input M1 input M2 input BYTE input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 CE input Input port P5 Input port P6 BUSY output SCLK input RXD input TXD output Input port P7 Input port P8 NMI input Input port P9 Input port P10 Input port P11 Power input Power input Power input Filter output fsc input pin for synchronized signal generating
I/O
Description Apply a 4.75 - 5.25 V voltage on the Vcc pin, and 0 V voltage on the Vss pin.
I I I I I I O
Connect to VCC. Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. Connect to VSS. Apply a 4.75 - 5.25 V voltage on the Vcc pin when built-in flash memory rewriting. Connect to VSS. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to X IN pin and open XOUT pin. Connect AVSS to VSS and AVCC to VCC, respectively. Enter the reference voltage for AD from this pin.
I I I I I I I I O I I O I I I I I O
Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. BUSY signal output pin Serial clock input pin Serial data input pin Serial data output pin Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Connect this pin to Vcc. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Open Connect VDD1 pin to VCC and connect VSS1 pin to VSS. Connect VDD2 pin to VCC and connect VSS2 pin to VSS. Connect VDD3 pin to VCC and connect VSS3 pin to VSS.
P85 P90 to P97 P100 to P107 P11 VDD1, VSS1 VDD2, VSS2 VDD3, VSS3 LP2 to LP4 FSCIN
O I I I
Open Subcarrier (fsc) input pin for synchronized signal generating. Input "L" level signal or open. Input pin of external compound video signal. Input "H" or "L" level signal or open. Slice voltage input pin at the time of slicing synchronized signal.
CVIN1, SYNCIN Composite video signal input SVREF Synchronous slice level input
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
VSS
P14 P15/INT3 P16/INT4 P17/INT5
VCC P31 P32 P33
VCC
P40 P41
P35
P34
P36
P22 P23
P11 P12
P21
P26 P27
P24 P25
VSS
P13
P07 P06 P05 P04 P03 P02 P01 P00
P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF
P10
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
P20
P30
P37
P42
88
58
57
56
55
54
53
52
51
50
49
48
47
46
45
89
P43 P44
P45 P46
90
91
92
93
P47 P50 P51 P52 P53 P54 P55 P56 P57/CLKOUT P60/CTS0/RTS0
P61/CLK0 P62/RXD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RXD1 P67/TXD1 P11/SLICEON M1
M2
VDD2 LP4 LP3 LP2 VSS2
CE
94
95
96
97
98
99
100
101
102
VSS
103
M306H2FCFP
44
43
42
41
40
39
38
37
104
105
BUSY SCLK RXD TXD VSS VPP VCC
VCC
AVCC P97/ADTRG/SIN4 VDD1 SYNCIN SVREF VSS1 VDD3 CVIN1 VSS3 FSCIN P96/ANEX1/SOUT4
106
107
108
109
110
111
112
113
114
115
116
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
36
35
34
33
32
31
30
VSS
P92/TB2IN/SOUT3 P91/TB1IN/SIN3
P87/XCIN P86/XCOUT
XOUT Vss
P95/ANEX0/CLK4
RESET
Vcc
P80/TA4OUT
RESET
VSS
Mode setup method Signal Value
VSS
VCC
Note 1: Connect oscillator circuit.
CNVss M1 RESET CE
Vcc Vss Vss Vcc Vcc
Figure 5.6.1. Pin connections for serial I/O mode (1)
VCC
P72/CLK2/TA1OUT P71/RXD2/SCL/TA0IN/TB5IN P70/TXD2/SDA/TA0OUT
P90/TB0IN/CLK3 BYTE
P94/DA1/TB4IN
P93/DA0/TB3IN
P81/TA4IN
P85/NMI
CNVss
P84/INT2 P83/INT1
XIN
P77/TA3IN P76/TA3OUT
P74/TA2OUT
Note 1
P73/CTS2/RTS2/TA1IN
P82/INT0
P75/TA2IN
Rev. 1.0
220
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.6.1 Overview of standard serial I/O mode 1 (clock synchronized) In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1). Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin. The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RTS1 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc.
Rev. 1.0
221
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.6.2 Software Commands Table 5.6.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Software commands are explained here below. Table 5.6.1. Software commands (Standard serial I/O mode 1)
Control command 1 Page read
1st byte transfer
2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (low)
3rd byte Address (high) Address (high) Address (high) SRD1 output
4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte
FF16
When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable
2
Page program
4116
3 4 5 6 7 8
Block erase Erase all blocks Read status register Clear status register ID check function Download function
2016 A716 7016 5016
Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high)
Address (high) Checksum Version data output Data output
9
Version data output function
FB16
ID1 To Data required input number of times Version Version data data output output Data output Data output
ID size
To ID7
Acceptable Not acceptable
10 Boot ROM area output function 11 Read check data
FC16
Version data output to 9th byte Data output to 259th byte
Acceptable Not acceptable Not acceptable
Check FD16 data (low)
Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.
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222
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the fall of the clock.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
FF16
A8 to A15
A16 to A23 data0 data255
Figure 5.6.2. Timing for page read Read Status Register Command This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
7016
SRD output
SRD1 output
Figure 5.6.3. Timing for reading the status register
Rev. 1.0
223
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Clear Status Register Command This command clears the bits (SR4-SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
5016
Figure 5.6.4. Timing for clearing the status register
Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is auto matically written. When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
4116
A8 to A15
A16 to A23
data0
data255
Figure 5.6.5. Timing for the page program
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224
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the optional even address of the specified block for addresses A8 to A23. When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
2016
A8 to A15
A16 to A23
D016
Figure 5.6.6. Timing for block erasing
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225
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Erase All Blocks Command This command erases the content of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the erase operation can be known by reading the status register.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
A716
D016
Figure 5.6.7. Timing for erasing all blocks Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
FA16
Data size (low)
Check sum
Program data
Program data
Data size (high)
Figure 5.6.8. Timing for download
Rev. 1.0
226
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
FB16
'V'
'E'
'R'
'X'
Figure 5.6.9. Timing for version information output
Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the fall of the clock.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
FC16
A8 to A15
A16 to A23
data0
data255
Figure 5.6.10. Timing for boot ROM area output
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227
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY)
F516
DF16
FF16
0F16
ID size
ID1
ID7
Figure 5.6.11. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB1
6
ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector
0FFFFC16 to 0FFFFF16
4 bytes
Figure 5.6.12. ID code storage addresses
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228
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. Check data adds write data in 1 byte units and obtains the two's-compliment of the insignificant 2 bytes of the accumulated data.
CLK1
RxD1 (M16C reception data) TxD1 (M16C transmit data)
FD16
Check data (low) RTS1(BUSY)
Check data (high)
Figure 5.6.13. Timing for the read check data
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229
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 5.6.2 gives the definition of each status register bit. After clearing the reset, the status register outputs "8016". Table 5.6.2. Status register (SRD) SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -
Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0". Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to "1". When the program status is cleared, it is set to "0".
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230
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 5.6.3 gives the definition of each status register 1 bit. "0016" is output when power is turned ON and the flag status is maintained even after the reset. Table 5.6.3. Status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Check sum match bit ID check completed bits Definition "1"
Update completed
"0" Not update Mismatch Not verified Verification mismatch Reserved Verified Normal operation -
Match 00 01 10 11 Time out -
SR9 (bit1) SR8 (bit0)
Data receive time out Reserved
Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. Check Sum Match Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Receive Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state.
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 5.6.14 shows a flowchart of the full status check and explains how to remedy errors which occur.
Read status register
SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES
YES
Command sequence error (Note 1)
Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used.
NO
Block erase error
NO
Program error
Should a program error occur, the block in error cannot be used.
End (block erase, program)
Note 1: Either SR5 or SR4 may become "0". Take care about it during program debugging. Note 2: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (501 6) before executing these commands. Figure 5.6.14. Full status check flowchart and remedial procedure for errors
Rev. 1.0
232
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Example Circuit Application for The Standard Serial I/O Mode 1 The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information.
Clock input BUSY output Data input Data output
CLK1 RTS1( BUSY) RXD1 TXD1 NMI
M306H2 Flash memory
CNVss
P50(CE)
VPP power source input
M2 M1 BYTE
(1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the Vpp power supply is supplied from an external source (writer). To use the user's power source, connect to 4.75V to 5.25 V. (3) In this example, microcomputer mode and standard serial I/O mode are changed with a switch.
Figure 5.6.15. Example circuit application for the standard serial I/O mode 1
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233
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.6.4 Overview of standard serial I/O mode 2 (clock asynchronized) In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1). Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level. The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Figure 5.6.16) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands. Initial communications with peripheral units After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 5.6.16). (1) Transmit "B016" from a peripheral unit. If the oscillation frequency input by the main clock is 10 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock.
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234
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Peripheral unit
MCU with internal flash memory Reset
(1) Transfer "B016" (2) Transfer "0016" 16 times At least 15ms transfer interval 15 th 16th
"B016" "B016" 1st 2nd "0016" "0016" "0016" "0016" "B016" (3) Transfer check code "B016" If the oscillation frequency input by the main clock is 10 MHz, the MCU outputs "B016". If other than 10 MHz, the MCU does not output anything.
The bit rate generator setting completes (9600bps)
Figure 5.6.16. Peripheral unit and initial communication How frequency is identified When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 10 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 5.6.4 gives the operation frequency and the baud rate that can be attained for.
Table 5.6.4 Operation frequency and the baud rate
Operation frequency (MHZ) 10MHZ 8MHZ 7.3728MHZ 6MHZ 5MHZ 4.5MHZ 4.194304MHZ 4MHZ 3.58MHZ 3MHZ 2MHZ Baud rate 9,600bps Baud rate 19,200bps - Baud rate 38,400bps - - - - - - Baud rate 57,600bps - - - - - -
: Communications possible - : Communications not possible
Rev. 1.0
235
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.6.5 Software Commands Table 5.6.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software commands of standard serial I/O mode 1. Software commands are explained here below. Table 5.6.5. Software commands (Standard serial I/O mode 2)
Control command 1 2 Page read Page program
1st byte transfer
2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (low)
3rd byte Address (high) Address (high) Address (high) SRD1 output
4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte
FF16 4116
When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable
3 4 5 6 7 8
Block erase Erase all unlocked blocks Read status register Clear status register ID check function Download function
2016 A716 7016 5016
Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high)
Address (high) Checksum Version data output Data output
9
Version data output function
FB16
ID1 To Data required input number of times Version Version data data output output Data output Data output
ID size
To ID7
Acceptable Not acceptable
10 Boot ROM area output function 11 Read check data
FC16
Version data output to 9th byte Data output to 259th byte
Acceptable Not acceptable Not acceptable
Check FD16 data (low)
12 Baud rate 9600 13 Baud rate 19200 14 Baud rate 38400 15 Baud rate 57600
B016 B116 B216 B316
B016 B116 B216 B316
Acceptable Acceptable Acceptable Acceptable
Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.
Rev. 1.0
236
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
FF16
A8 to A15 A16 to A23
data0
data255
Figure 5.6.17. Timing for page read Read Status Register Command This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
7016
SRD output
SRD1 output
Figure 5.6.18. Timing for reading the status register
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237
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Clear Status Register Command This command clears the bits (SR4-SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
5016
Figure 5.6.19. Timing for clearing the status register
Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with ad dresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
4116
A8 to A15 A16 to A23
data0
data255
Figure 5.6.20. Timing for the page program
Rev. 1.0
238
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the optional even address of the specified block for addresses A8 to A23. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register.
RxD1
(M16C received data)
2016
A8 to A15 A16 to A23
D016
TxD1
(M16C transmitted data)
Figure 5.6.21. Timing for block erasing
Erase All Blocks Command This command erases the content of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. The result of the erase operation can be known by reading the status register.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
A716
D016
Figure 5.6.22. Timing for erasing all blocks
Rev. 1.0
239
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
FA16
Data size (lower)
Data size (upper)
checksum
program data
program data
Figure 5.6.23. Timing for download
Rev. 1.0
240
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
FB16
'V'
'E'
'R'
'X'
Figure 5.6.24. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
FC16
A8 to A15 A16 to A23
data0
data255
Figure 5.6.25. Timing for boot ROM area output
Rev. 1.0
241
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
F516
DF16
FF16
0F16
ID size
ID1
ID7
Figure 5.6.26. Timing for the ID check
ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector
4 bytes
Figure 5.6.27. ID code storage addresses
Rev. 1.0
242
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. Check data adds write data in 1 byte units and obtains the two's-compliment of the insignificant 2 bytes of the accumulated data.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
FD16
Data size (lower)
Data size (upper)
Figure 5.6.28. Timing for the read check data
Baud Rate 9600 This command changes baud rate to 9,600 bps. Execute it as follows. (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
B016
B016
Figure 5.6.29. Timing of baud rate 9600
Rev. 1.0
243
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Baud Rate 19200 This command changes baud rate to 19,200 bps. Execute it as follows. (1) Transfer the "B116" command code with the 1st byte. (2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
B116
B116
Figure 5.6.30. Timing of baud rate 19200
Baud Rate 38400 This command changes baud rate to 38,400 bps. Execute it as follows. (1) Transfer the "B216" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
B216
B216
Figure 5.6.31. Timing of baud rate 38400
Baud Rate 57600 This command changes baud rate to 57,600 bps. Execute it as follows. (1) Transfer the "B316" command code with the 1st byte. (2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.
RxD1 (M16C reception data) TxD1 (M16C transmit data)
B316
B316
Figure 5.6.32. Timing of baud rate 57600
Rev. 1.0
244
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.6.6 Example Circuit Application for The Standard Serial I/O Mode 2 The below figure shows a circuit application for the standard serial I/O mode 2.
CLK1 Monitor output Data input Data output BUSY RXD1 TXD1 NMI
M306H2 Flash memory
CNVss
P50(CE)
VPP power source input
M2 M1 BYTE
(1) In this example, the Vpp power supply is supplied from an external source (writer). To use the user's power source, connect to 4.75V to 5.25 V. (2) In this example, microcomputer mode and standard serial I/O mode are changed with a switch.
Figure 5.6.23. Example circuit application for the standard serial I/O mode 2
Rev. 1.0
245
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
5.7 Electrical Characteristics
Table 5.7.1 Absolute maximum ratings
Symbol Vcc AVcc M2 Parameter Supply voltage Analog supply voltage Supply voltage for program/erase RESET, CNVSS, BYTE, Input P00 to P07, P10 to P17, P20 to P27, P30 to P37, voltage P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, VREF, XIN, M1 P70, P71 Output voltage VO P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, XOUT, P11 P70, P71, Ta=25 C Power dissipation Operating ambient temperature (Note) Storage temperature Condition VCC=AVCC VCC=AVCC Rated value - 0.3 to 5.75 - 0.3 to 5.75 - 0.3 to 5.75 Unit V V V
VI
- 0.3 to Vcc+0.3
V
- 0.3 to 5.75
V
- 0.3 to Vcc+0.3
V
Pd Topr Tstg
- 0.3 to 5.75 1000 25 5 - 40 to 125
V mW C C
Note: It is a value in flash memory mode. Other parameter becomes same as a value in microcomputer mode.
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
Table 5.7.2 DC electrical characteristics (referenced to VCC = 5.0V at Ta = 25oC unless otherwise specified)
Symbol
IPP1 IPP2 IPP3 VPP
Parameter
VPP power supply current (at read) VPP power supply current (at program) VPP power supply current (at erase) VPP power supply voltage VPP =VCC VPP =VCC VPP =VCC
Condition
Rated value
Min. Typ. Max. 100 60 70 4.75 5.25
Unit
A mA mA V
Rev. 1.0
247
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
6. PACKAGE OUTLINE
116P6A-A
MMP
JEDEC Code - Weight(g) 1.78 Lead Material Cu Alloy
Plastic 116pin 2020mm body LQFP
MD
EIAJ Package Code LQFP116-P-2020-0.65
e
HD D
116 1 88
Recommended Mount Pad
87
b2
l2
Symbol A A1 A2 b c D E e HD HE L L1 Lp
29 30 58
59
A F L1
e
A2
A3
A3
x y b2 I2 MD ME
A1
y
b
x
M
L Lp Detail F
Dimension in Millimeters Min Nom Max 1.7 - - 0.125 0.2 0.05 1.4 - - 0.17 0.22 0.27 0.105 0.125 0.175 19.9 20.0 20.1 19.9 20.0 20.1 0.65 - - 21.8 22.0 22.2 21.8 22.0 22.2 0.35 0.5 0.65 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.13 0.1 - - 0 8 - 0.225 - - 0.95 - - - 20.4 - - 20.4 -
E HE
c
ME
Rev. 1.0
248
MITSUBISHI MICROCOMPUTERS
M306H2FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER
7. DIFFERENCES BETWEEN M306H2MC-XXXFP AND M306H2FCFP
Item Processor mode M306H2MC-XXXFP Single-chip mode Memory extension mode Microprocessor mode(Note 1) Mask ROM M1: Test input (Connect it to the VSS pin.) M2: Test input (Connect it to the VSS pin.) CNVSS pin function This pin switches between processor modes. M306H2FCFP Single-chip mode Memory expansion mode
ROM type M1/M2 pin function
Flash memory M1: Chip mode setting input (Note 2)
M2: Flash memory rewriting power supply input
Normally connect it to the VSS pin.(Note 2)
BYTE pin function
This pin switches between external data buses. This pin switches between external data buses. (Note 3)
Notes 1: Microprocessor mode can be used only on M306H2MC-XXXFP. 2: These pins are used to control flash memory mode. For more information, consult M306H2FCFP flash memory specifications. 3 :When use flash memory mode (parallel I/O, standard serial I/O and CPU rewriting mode), connect with VSS pin. 4 :Since it differs in part about an electrical characteristics, check the specification of M306H2MC-XXXFP and M306H2FCFP. 5 :There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version.
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249
REVISION HISTORY
Rev. No. 1.0 PDF First Edition
M306H2FCFP (Rev.1.0) DATA SHEET
Revision Description Rev. date 0202
(1/1)

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